Kyungmin Park wrote:
>
> Hi,
>
[...]
> >
> > +config ARCH_EXYNOS5
> > + bool "SAMSUNG EXYNOS5"
> > + select HAVE_SMP
> > + help
> > + Samsung EXYNOS5 (Cortex-A15) SoC based systems
> This config is located at choice. It means it can't build the exynos4
> and exynos5 simultaneously. I'm not sure it's acceptable for mainline.
See Arnd's comments.
[...]
> > +obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
> Where's clock-exynos5.c file in this patch?. maybe it's another patch.
See 3rd patch.
[...]
> > +void exynos5_restart(char mode, const char *cmd)
> > +{
> > + __raw_writel(0x1, EXYNOS_SWRESET);
> > +}
> Why new restart is required? it's same S5P_SWRESET and EXYNOS_SWRESET.
> see below.
It will be updated for exynos5.
[...]
> >
> > #define S5P_SWRESET S5P_PMUREG(0x0400)
> > +#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
> Please use just one.
>
See above.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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