This patch series changes the way PLL clocks are registered, mainly to
add validation of rate tables. What follows is a list of changes
introduced by the patch:
 - Validation of PLL rate tables
 - Added support for heterogenous rate tables.
 - Removed explicit dependency on the input clock source at
   the driver initialization
 - Keeping tables sorted is no longer needed
 - PLL initialization data is now marked as __initconst

For more details, please refer to:
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35072.html


Humberto Silva Naves (2):
  clk: samsung: Add validation of rate tables for the PLL clocks
  clk: samsung: Make pll initialization structures read-only.

 drivers/clk/samsung/clk-exynos3250.c | 105 +++++-----
 drivers/clk/samsung/clk-exynos4.c    | 146 ++++++-------
 drivers/clk/samsung/clk-exynos5250.c |  78 +++----
 drivers/clk/samsung/clk-exynos5260.c | 104 +++++-----
 drivers/clk/samsung/clk-exynos5410.c |   2 +-
 drivers/clk/samsung/clk-exynos5420.c |  52 +++--
 drivers/clk/samsung/clk-pll.c        | 387 ++++++++++++++++++++++++++---------
 drivers/clk/samsung/clk-pll.h        |  30 +--
 drivers/clk/samsung/clk-s3c2410.c    | 142 ++++++-------
 drivers/clk/samsung/clk-s3c2412.c    |   2 +-
 drivers/clk/samsung/clk-s3c2443.c    |   4 +-
 drivers/clk/samsung/clk-s3c64xx.c    |   2 +-
 12 files changed, 600 insertions(+), 454 deletions(-)

-- 
2.0.1

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