On 11/29/2014 11:18 PM, Kukjin Kim wrote:
Tobias Jakobi wrote:
EXYNOS4_MCT_L_MASK is defined as 0xffffff00, so applying this bitmask
produces a number outside the range 0x00 to 0xff, which always results
in execution of the default switch statement.
Obviously this is wrong and git history shows that the bitmask inversion
was incorrectly set during a refactoring of the MCT code.
Fix this by putting the inversion at the correct position again.
Reported-by: GP Orcullo <kinsama...@gmail.com>
Signed-off-by: Tobias Jakobi <tjak...@math.uni-bielefeld.de>
+ Daniel, Thomas,
adding Doug's review tag from previous his reply.
Reviewed-by: Doug Anderson <diand...@chromium.org>
And
Acked-by: Kukjin Kim <kgene....@samsung.com>
Daniel,
Since this is obvious fix, can you please pick into your tree?
If any problem, please kindly let me know.
Hi Kukjin,
the patch is my tree for a 3.18 fix.
Added the stable@ also in the Cc list.
Thanks
-- Daniel
---
drivers/clocksource/exynos_mct.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9403061..83564c9 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -97,8 +97,8 @@ static void exynos4_mct_write(unsigned int value, unsigned
long offset)
writel_relaxed(value, reg_base + offset);
if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
- stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
- switch (offset & EXYNOS4_MCT_L_MASK) {
+ stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
+ switch (offset & ~EXYNOS4_MCT_L_MASK) {
case MCT_L_TCON_OFFSET:
mask = 1 << 3; /* L_TCON write status */
break;
--
2.0.4
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