Follow your hint, Doug, I have downloaded from OXSEMI the
OX16C950 Datasheet R2.2 - July 1999
and the
OX16C950/2/4 APPLICATION NOTES Version 1.0(16 August 1999)
In the latter I found under
3.1.3 950 Specific Register Access
an offset table:
Offset Register Description
001 ASR Additional Status Register
011 RFL Receiver FIFO Fill Level (0-128)
100 TFL Transmitter FIFO Fill Level (0-128)
101 ICR Index Control Register ...
So I am sure the values in serial_reg.h are correct, the comments
have to change the lines.
Thanks, winfried
On Tue, Jan 18, 2000 at 07:34:00AM -0500, Doug McNash wrote:
=>
=> The bits probably select (I'm not looking at the code) from a table where
=> say, 0x03 => 8d and 0x04 => 120d and define the point where the UART
=> interrupts to
=> request filling or empting the fifo.
=>
=> Refer to the UART data sheet.
=>
=> >
=> > The following lines I have found in 'serial-4.91/serial_reg.h'.
=> >
=> > #define UART_RFL 0x03 /* Transmitter FIFO level */
=> > #define UART_TFL 0x04 /* Receiver FIFO level */
=> >
=>
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