> From [EMAIL PROTECTED] Mon Jan 25 14:18:23 1999
>
> On Mon, 25 Jan 1999, Sketch wrote:
>
> > On Mon, 25 Jan 1999, Robert M. Hyatt wrote:
> >
> > > its a manufacturing issue. They don't do a special 333 (or 366) mhz
> > > L2 for the celeron, they use the stock PII cache with 128kb rather than
> > > 512kb. Saves money by using economy of scale in production. IE it is
> > > cheaper to make 400mhz 128kb L2 modules than it is to make some 400mhz
> >
> > It is a manufacturing issue, but that is somewhat incorrect.
> >
> > The PII uses external cache chips in the same "CPU module".
> > The Celeron uses on-die cache that is integrated into the CPU core.
>
> this means the Celeron has a L1 _and_ L2 cache on the processor
> die? That is certainly something contrary to every other processor
> with L2 they have built (ie the pentium pro, and PII's).
Yup.
> >
> > I suspect that the reason is that most Celerons are good for 400MHz or so,
> > but Intel didn't want to cut into their profits of PII's at faster
> > clockspeeds. Now that the PIII is due out soon, Intel has released
> > Celerons at higher clock speeds. They are also undercutting AMD's prices
> > on K6-2's. Making less money for your products is better than someone
> > else getting it instead, no?
>
> very likely true... marketing always wins over engineers.. :)
I'm looking forward to seeing mention of this in the antitrust case
against Intel. They're effectively selling "higher end" products into
the low end market, but attempting to disable them such that they won't
cut into their fat margins on products that are effectively more
expensive to produce and generally poorer performers...all to force
the bottom feeders out of their market.
A celeron 300a clocked to 450mhz often outperforms a real 450. You'd
probably see manufacturers like Abit producing dual PPGA boards prehacked
to allow dual celerons if they weren't afraid of their BX chipset allocation
suddenly going away.
Regards,
Chris
--
Christopher Mauritz
[EMAIL PROTECTED]
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