> >> >Dunno about the cache issues - to be honest I don't know why different >> >page layouts in physical RAM makes such a big difference... >> > > >> Maybe TLB misses? > >That's what I thought, but it was pointed out to me that TLB refils >for x86 are done in hardware and are pretty fast. Upon investigation >it turned out to be L2 cache misses due to cache line aliasing. >Note that the cache will cache physical memory, hence the layout of >physical pages matters much. > >The solution: page colouring (thanks to DaveM for his tips). I tried >that and it works. The patch is crude and can slow down process >startup times, and it requires a system with plenty of RAM to spare, >but it does work. If people want to try this, I could be encouraged to >post a patch. Yes I would like to try this on some of our numeric codes. Robert is quite right -- trying to optimize code the way things are now is difficult. Emil - Linux SMP list: FIRST see FAQ at http://www.irisa.fr/prive/mentre/smp-faq/ To Unsubscribe: send "unsubscribe linux-smp" to [EMAIL PROTECTED]
