This is a note to let you know that I've just added the patch titled
mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS
to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mm-zsmalloc-prepare-to-variable-max_physmem_bits.patch
and it can be found in the queue-4.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <sta...@vger.kernel.org> know about it.
>From foo@baz Thu Nov 4 09:33:05 AM CET 2021
From: Florian Fainelli <f.faine...@gmail.com>
Date: Wed, 3 Nov 2021 13:57:03 -0700
Subject: mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS
To: linux-ker...@vger.kernel.org
Cc: sta...@vger.kernel.org, Greg Kroah-Hartman <gre...@linuxfoundation.org>,
Sasha Levin <sas...@kernel.org>, "Kirill A. Shutemov"
<kirill.shute...@linux.intel.com>, Nitin Gupta <ngu...@vflare.org>, Minchan Kim
<minc...@kernel.org>, Andy Lutomirski <l...@amacapital.net>, Borislav Petkov
<b...@suse.de>, Linus Torvalds <torva...@linux-foundation.org>, Peter Zijlstra
<pet...@infradead.org>, Sergey Senozhatsky <sergey.senozhatsky.w...@gmail.com>,
Thomas Gleixner <t...@linutronix.de>, linux...@kvack.org, Ingo Molnar
<mi...@kernel.org>, Florian Fainelli <f.faine...@gmail.com>, Vineet Gupta
<vgu...@synopsys.com>, Russell King <li...@armlinux.org.uk>, Ralf Baechle
<r...@linux-mips.org>, Benjamin Herrenschmidt <b...@kernel.crashing.org>, Paul
Mackerras <pau...@samba.org>, Michael Ellerman <m...@ellerman.id.au>, Ingo
Molnar <mi...@redhat.com>, "H. Peter Anvin" <h...@zytor.com>, x...@kernel.org
(maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), Arnd Bergmann
<a...@arndb.de>, Stefan Agner <stefan@agn
er.ch>, Thomas Bogendoerfer <tsbog...@alpha.franken.de>, Mike Rapoport
<r...@linux.ibm.com>, linux-snps-arc@lists.infradead.org (open list:SYNOPSYS
ARC ARCHITECTURE), linux-arm-ker...@lists.infradead.org (moderated list:ARM
PORT), linux-m...@linux-mips.org (open list:MIPS),
linuxppc-...@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND
64-BIT)), linux-a...@vger.kernel.org (open list:GENERIC INCLUDE/ASM HEADER
FILES)
Message-ID: <20211103205704.374734-2-f.faine...@gmail.com>
From: "Kirill A. Shutemov" <kirill.shute...@linux.intel.com>
commit 02390b87a9459937cdb299e6b34ff33992512ec7 upstream
With boot-time switching between paging mode we will have variable
MAX_PHYSMEM_BITS.
Let's use the maximum variable possible for CONFIG_X86_5LEVEL=y
configuration to define zsmalloc data structures.
The patch introduces MAX_POSSIBLE_PHYSMEM_BITS to cover such case.
It also suits well to handle PAE special case.
Signed-off-by: Kirill A. Shutemov <kirill.shute...@linux.intel.com>
Reviewed-by: Nitin Gupta <ngu...@vflare.org>
Acked-by: Minchan Kim <minc...@kernel.org>
Cc: Andy Lutomirski <l...@amacapital.net>
Cc: Borislav Petkov <b...@suse.de>
Cc: Linus Torvalds <torva...@linux-foundation.org>
Cc: Peter Zijlstra <pet...@infradead.org>
Cc: Sergey Senozhatsky <sergey.senozhatsky.w...@gmail.com>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: linux...@kvack.org
Link:
http://lkml.kernel.org/r/20180214111656.88514-3-kirill.shute...@linux.intel.com
Signed-off-by: Ingo Molnar <mi...@kernel.org>
Signed-off-by: Florian Fainelli <f.faine...@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
---
arch/x86/include/asm/pgtable-3level_types.h | 1 +
arch/x86/include/asm/pgtable_64_types.h | 2 ++
mm/zsmalloc.c | 13 +++++++------
3 files changed, 10 insertions(+), 6 deletions(-)
--- a/arch/x86/include/asm/pgtable-3level_types.h
+++ b/arch/x86/include/asm/pgtable-3level_types.h
@@ -44,5 +44,6 @@ typedef union {
*/
#define PTRS_PER_PTE 512
+#define MAX_POSSIBLE_PHYSMEM_BITS 36
#endif /* _ASM_X86_PGTABLE_3LEVEL_DEFS_H */
--- a/arch/x86/include/asm/pgtable_64_types.h
+++ b/arch/x86/include/asm/pgtable_64_types.h
@@ -40,6 +40,8 @@ typedef struct { pteval_t pte; } pte_t;
#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
#define P4D_MASK (~(P4D_SIZE - 1))
+#define MAX_POSSIBLE_PHYSMEM_BITS 52
+
#else /* CONFIG_X86_5LEVEL */
/*
--- a/mm/zsmalloc.c
+++ b/mm/zsmalloc.c
@@ -83,18 +83,19 @@
* This is made more complicated by various memory models and PAE.
*/
-#ifndef MAX_PHYSMEM_BITS
-#ifdef CONFIG_HIGHMEM64G
-#define MAX_PHYSMEM_BITS 36
-#else /* !CONFIG_HIGHMEM64G */
+#ifndef MAX_POSSIBLE_PHYSMEM_BITS
+#ifdef MAX_PHYSMEM_BITS
+#define MAX_POSSIBLE_PHYSMEM_BITS MAX_PHYSMEM_BITS
+#else
/*
* If this definition of MAX_PHYSMEM_BITS is used, OBJ_INDEX_BITS will just
* be PAGE_SHIFT
*/
-#define MAX_PHYSMEM_BITS BITS_PER_LONG
+#define MAX_POSSIBLE_PHYSMEM_BITS BITS_PER_LONG
#endif
#endif
-#define _PFN_BITS (MAX_PHYSMEM_BITS - PAGE_SHIFT)
+
+#define _PFN_BITS (MAX_POSSIBLE_PHYSMEM_BITS - PAGE_SHIFT)
/*
* Memory for allocating for handle keeps object position by
Patches currently in stable-queue which might be from f.faine...@gmail.com are
queue-4.14/mm-zsmalloc-prepare-to-variable-max_physmem_bits.patch
queue-4.14/arch-pgtable-define-max_possible_physmem_bits-where-needed.patch
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