On 3/28/24 06:57, Mathieu Desnoyers wrote:
> On 2024-03-28 01:39, Vineet Gupta wrote:
>> Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing()
>> across all architectures")
>>
>> Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
>> at least).
>>
>> Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
>> PAGE_SIZE) however recently that support was ripped out so VIPT aliasing
>> cache is not relevant to ARC anymore.
>>
>> P.S. : This has been discussed a few times on lists [1]
>> P.S.2: Please CC the arch maintainers and/or mailing list before adding
>> such interfaces.
> Because 8690bbcf3b70 was introducing a tree-wide change affecting all
> architectures, I CC'd linux-a...@vger.kernel.org. I expected all
> architecture maintainers to follow that list, which is relatively
> low volume.
Ideally yeah arch maintainers should be lurking there.
> I'm sorry that you learn about this after the fact as a result.
Please don't be, no harm done, the fix was easy ;-)
> My intent was to use the list rather than CC about 50 additional
> people/mailing lists.
That is true but I don't think maintainers mind that in general. I still
posit that any new interfaces to arch code should be explicitly run by them.
> Of course, if VIPT aliasing is removed from ARC, removing the
> config ARCH_HAS_CPU_CACHE_ALIASING and using the generic
> cpu_dcache_is_aliasing() is the way to go. Feel free to add
> my:
>
> Acked-by: Mathieu Desnoyers <mathieu.desnoy...@efficios.com>
Thx,
-Vineet
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