[Cc parisc, sparc32, arc and hexagon] On Thu, Dec 18, 2025 at 06:37:38AM +0900, FUJITA Tomonori wrote: > This adds atomic xchg helpers with full, acquire, release, and relaxed > orderings in preparation for i8/i16 atomic xchg support. > > The architectures supporting Rust, implement atomic xchg families > using architecture-specific instructions. So the helpers just call > them. > > Note that the architectures that support Rust handle xchg differently: > > - arm64 and riscv support xchg with all the orderings. > > - x86_64 and loongarch support only full-ordering xchg. They calls the > full-ordering xchg for any orderings. > > - arm v7 supports only relaxed-odering xchg. It uses __atomic_op_ > macros to add barriers properly. >
Thanks for the work! And please do Cc linux-arch next time when doing architecture-related changes. We would get more experts to take a look. I think the current implementation expects that xchg() work with normal store/load, and that requires ARCH_SUPPORTS_ATOMIC_RMW. So could you add a comment saying the current implementation only support ARCH_SUPPORTS_ATOMIC_RMW architectures? And when you wire up the rust helpers, I think using #[cfg(CONFIG_ARCH_SUPPORTS_ATOMIC_RMW)] is a good idea. This will at least let the !ARCH_SUPPORTS_ATOMIC_RMW archs know that something is missing here. Regards, Boqun > FUJITA Tomonori (4): > rust: helpers: Add i8/i16 atomic xchg helpers > rust: helpers: Add i8/i16 atomic xchg_acquire helpers > rust: helpers: Add i8/i16 atomic xchg_release helpers > rust: helpers: Add i8/i16 atomic xchg_relaxed helpers > > rust/helpers/atomic_ext.c | 41 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > > base-commit: 02c5c8c11bbd34cdd9c566dd4ecca48995c09621 > -- > 2.43.0 > _______________________________________________ linux-snps-arc mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-snps-arc
