Hi all,
Some feedback based on my tests of the HW randomizer available in the
NFC controller
(you might already know what I found :-)):
- the HW randomizer uses a Fibonacci LFSR with the x^15 + x^14 + 1
feedback polynomial
(see http://en.wikipedia.org/wiki/Linear_feedback_shift_register for
more informations
on LFSR)
- the NFC controller resets the LSFR state each time a new TRANSFER CMD
is launched.
In my driver this means the LFSR is resetted to the specified SEED
value on each ECC step
size block transfer. I'm not sure this is the case for PAGE CMDs, did
someone already
checked this ?
The Fibonacci LFSR is pretty simple to implement, and I should be able
to propose a generic
interface to support randomizers in the NAND core code (including a SW
implementation of
a Fibonacci LFSR and the sunxi HW one) in the same way ECC handling is
exposed...
I'd also like to have your opinion on some of my reflexions.
If I understand correctly (tell me if I'm wrong), some MLC NANDs need to
scramble DATA
to avoid spurious bitflips when writing the same pattern on NAND pages
(see
http://etrij.etri.re.kr/Cyber/Download/PublishedPaper/3501/etrij.feb2013.0166.pdf).
The bitflips occurs when writing or reading on pages. These bitflips
always appears on pages
of the block being read or written, right ?
I guess this is why the base sunxi driver uses a seed table (to avoid
similar patterns on different
pages of a given block when writting the same pattern on the whole block).
Please tell me if you think I'm mistaken (I'm new to this whole MLC NAND
things).
I also thought about a nice way to define the randomizer seed table from
the DT(instead of
statically embedding it in the sunxi driver).
Here's what I came with:
nfc@xxx {
nand@0 {
allwinner,nand-randomizer-seeds = <A B C ...>;
};
};
The boot0 partition problem still remains, as the seed table differs in
this specific partition (always
uses 0x4A80)...
To solve this we might consider defining the seed table per partition
instead of defining it for the
whole flash.
Please feel free to share you knowledge and thoughts.
Best Regards,
Boris
On 15/01/2014 10:51, Boris BREZILLON wrote:
Hello,
This series add the sunxi NFC support with up to 8 NAND chip connected.
I'm still in the early stages drivers development and some key features are
missing, but it's usable (I tested it on the cubietruck board).
Here's what's missing:
- DMA support
- HW randomization support
- many more improvements
This series depends on Emilio's patch series implementing mod0 clks
(http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/185478.html)
+ an other patch not yet posted
(http://git.elopez.com.ar/linux/commits/5b4eb3ac406b9c98965714d40e8dd6da943d1ab0)
This a pre v2 version (some rework asked by Jason Gunthorpe are not integrated
yet), hence why I only send this series to the sunxi dev ML.
Best Regards,
Boris
Changes since v1:
- add HW ECC support
Boris BREZILLON (11):
mtd: nand: retrieve ECC requirements from Hynix READ ID byte 4
mtd: nand: define struct nand_timings
of: mtd: add NAND timings retrieval support
of: mtd: add NAND timings bindings documentation
mtd: nand: add sunxi NFC support
mtd: nand: add sunxi NFC dt bindings doc
ARM: dt/sunxi: add NFC node to Allwinner A20 SoC
ARM: dt/sunxi: add NFC pinctrl pin definitions
ARM: sunxi/dt: enable NAND on cubietruck board
mtd: nand: add sunxi HW ECC support
ARM: sunxi/dt: enable HW ECC on cubietruck board
Documentation/devicetree/bindings/mtd/nand.txt | 34 +
.../devicetree/bindings/mtd/sunxi-nand.txt | 78 ++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 31 +
arch/arm/boot/dts/sun7i-a20.dtsi | 35 +
drivers/mtd/nand/Kconfig | 6 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/nand_base.c | 37 +
drivers/mtd/nand/sunxi_nand.c | 957 ++++++++++++++++++++
drivers/of/of_mtd.c | 47 +
include/linux/mtd/nand.h | 44 +
include/linux/of_mtd.h | 9 +
11 files changed, 1279 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/sunxi-nand.txt
create mode 100644 drivers/mtd/nand/sunxi_nand.c
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