On Saturday, February 15, 2014 7:29:01 PM UTC, Siarhei Siamashka wrote: > Based on reading the A20 user manual, it looks like the same > single PLE/PERFMU IRQ is supposed to be used for the CPU > performance counters as on Allwinner A10. This is already suspicious, > because normally each CPU core in a dual-core system should have > its own performance monitoring unit IRQ as explained in: > > http://thread.gmane.org/gmane.linux.ports.arm.kernel/181392/focus=181597 > > Still assuming that this is the case and borrowing the code > from db8500 does not work. No interrupts are arriving at all. > > Is there anything special needed to make sure that the performance > monitoring unit interrupts are routed correctly on Allwinner A20? > > Now that Cortex-A7 and GIC are both ARM IP, one might assume that > they perhaps should be able to play nicely together without > involving anything that is Allwinner specific. > > Any ideas? The perf/oprofile tools are very useful for identifying > performance bottlenecks and optimizing software. They work nicely > on Allwinner A10. It would be great if Allwinner A20 could be > supported too.
The lack of perf support on this chip is becoming increasingly annoying to me as well. I'd be happy to help get it working in any way I can. -- Mans Rullgard -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
