RDIV is lacking a set of brackets compared with DIV_ROUND_UP but due to precedence rules things work out the same for all callers.
Confirmed with objdump before and after. Signed-off-by: Ian Campbell <[email protected]> --- arch/arm/cpu/armv7/sunxi/clock.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c index 980fb90..a344971 100644 --- a/arch/arm/cpu/armv7/sunxi/clock.c +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -109,7 +109,6 @@ int clock_twi_onoff(int port, int state) #define PLL1_CFG(N, K, M, P) (1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \ 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \ (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0) -#define RDIV(a, b) ((a + (b) - 1) / (b)) struct { u32 pll1_cfg; @@ -146,8 +145,8 @@ void clock_set_pll1(int hz) hz = pll1_para[i].freq; /* Calculate system clock divisors */ - axi = RDIV(hz, 432000000); /* Max 450MHz */ - ahb = RDIV(hz/axi, 204000000); /* Max 250MHz */ + axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ + ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ apb0 = 2; /* Max 150MHz */ printf("CPU: %dHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); -- 1.9.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
