This discouples the actual mmc clock rate we get from the ram speed, which leads to getting exact clockspeeds for mmc rather then something approximately right.
As an added bonus this makes things easier on sun6i since pll5 cannot be used as a module source at all there. This has been tested on sun4i, sun5i and sun7i. Signed-off-by: Hans de Goede <[email protected]> --- drivers/mmc/sunxi_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1c71bfc..3adb151 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -204,10 +204,10 @@ static int mmc_clk_io_on(int sdc_no) writel(rval, &ccm->ahb_gate0); /* config mod clock */ - pll_clk = clock_get_pll5(); + pll_clk = clock_get_pll6(); /* should be close to 100 MHz but no more, so round up */ divider = ((pll_clk + 99999999) / 100000000) - 1; - writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL5 | divider, + writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider, mmchost->mclkreg); mmchost->mod_clk = pll_clk / (divider + 1); -- 1.9.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
