Hi,
On 04/13/2014 09:56 PM, Ian Campbell wrote:
> In some cases we are setting all of the defined bits of the configuration
> register, so there is no need for a read/modify/write via either sr32 or
> clrsetbits, just write the value we need.
>
> Tested on Cubietruck (sun7i) and compile tested only for Colombus (sun6i).
>
> Having made these changes sr32 is now unused in sunxi so remove the prototype.
>
> Signed-off-by: Ian Campbell <[email protected]>
Thanks, review below.
> ---
> arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 15 ++++++++++-----
> arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 18 ++++++++++++------
> arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 20 +++++++++++++++++---
> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 20 +++++++++++++++++---
> arch/arm/include/asm/arch-sunxi/sys_proto.h | 1 -
> 5 files changed, 56 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
> b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
> index a6bdd1a..52d1989 100644
> --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
> +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
> @@ -49,12 +49,14 @@ void clock_init_uart(void)
> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>
> /* uart clock source is apb1 */
> - sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
> - sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
> - sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);
> + writel(APB1_CLK_SRC_OSC24M|
> + APB1_CLK_RATE_N_1|
> + APB1_CLK_RATE_M(1),
> + &ccm->apb1_clk_div_cfg);
>
> /* open the clock for uart */
> - sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
> + setbits_le32(&ccm->apb1_gate,
> + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
> }
>
> int clock_twi_onoff(int port, int state)
> @@ -66,7 +68,10 @@ int clock_twi_onoff(int port, int state)
> return -1;
>
> /* set the apb clock gate for twi */
> - sr32(&ccm->apb1_gate, 0 + port, 1, state);
> + state = (state ? CLK_GATE_OPEN : CLK_GATE_CLOSE);
> + clrsetbits_le32(&ccm->apb1_gate,
> + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port),
> + state << (APB1_GATE_TWI_SHIFT+port));
>
> return 0;
> }
I would prefer to see this as something like this:
if (state)
setbits_le32(&ccm->apb1_gate, CLK_GATE_OPEN <<
(APB1_GATE_TWI_SHIFT+port));
else
clrbits_le32(&ccm->apb1_gate, CLK_GATE_OPEN <<
(APB1_GATE_TWI_SHIFT+port));
> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> index c8886b9..5acbff9 100644
> --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> @@ -58,15 +58,18 @@ void clock_init_uart(void)
> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>
> /* uart clock source is apb2 */
> - sr32(&ccm->apb2_div, 24, 2, APB2_CLK_SRC_OSC24M);
> - sr32(&ccm->apb2_div, 16, 2, APB2_FACTOR_N);
> - sr32(&ccm->apb2_div, 0, 5, APB2_FACTOR_M);
> + writel(APB2_CLK_SRC_OSC24M|
> + APB2_CLK_RATE_N_1|
> + APB2_CLK_RATE_M(1),
> + &ccm->apb2_div);
>
> /* open the clock for uart */
> - sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
> + setbits_le32(&ccm->apb2_gate,
> + CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
>
> /* deassert uart reset */
> - sr32((u32 *)SUN6I_ABP2_RESET_BASE, 16 + CONFIG_CONS_INDEX - 1, 1, 1);
> + setbits_le32((u32 *)SUN6I_ABP2_RESET_BASE,
> + 1 << (16 + CONFIG_CONS_INDEX - 1));
>
> /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
> writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
> @@ -81,7 +84,10 @@ int clock_twi_onoff(int port, int state)
> return -1;
>
> /* set the apb clock gate for twi */
> - sr32(&ccm->apb2_gate, 0 + port, 1, state);
> + state = (state ? CLK_GATE_OPEN : CLK_GATE_CLOSE);
> + clrsetbits_le32(&ccm->apb2_gate,
> + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port),
> + state << (APB2_GATE_TWI_SHIFT+port));
>
> return 0;
> }
idem.
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
> index a85d541..85ae8d7 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
> @@ -91,9 +91,23 @@ struct sunxi_ccm_reg {
> };
>
> /* apb1 bit field */
> -#define APB1_CLK_SRC_OSC24M 0
> -#define APB1_FACTOR_M 0
> -#define APB1_FACTOR_N 0
> +#define APB1_CLK_SRC_OSC24M (0x0<<24)
> +#define APB1_CLK_SRC_PLL6 (0x1<<24)
> +#define APB1_CLK_SRC_LOSC (0x2<<24)
> +#define APB1_CLK_SRC_MASK (0x3<<24)
> +#define APB1_CLK_RATE_N_1 (0x0<<16)
> +#define APB1_CLK_RATE_N_2 (0x1<<16)
> +#define APB1_CLK_RATE_N_4 (0x2<<16)
> +#define APB1_CLK_RATE_N_8 (0x3<<16)
> +#define APB1_CLK_RATE_N_MASK (3<<16)
> +#define APB1_CLK_RATE_M(m) (((m)-1)<<0)
> +#define APB1_CLK_RATE_M_MASK (0x1f<<0)
> +
> +/* apb1 gate field */
> +#define APB1_GATE_UART_SHIFT (16)
> +#define APB1_GATE_UART_MASK (0xff<<APB1_GATE_UART_SHIFT)
> +#define APB1_GATE_TWI_SHIFT (0)
> +#define APB1_GATE_TWI_MASK (0xf<<APB1_GATE_TWI_SHIFT)
>
> /* clock divide */
> #define AXI_DIV_SHIFT (0)
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index 1d15c4d..a6b69a8 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -137,9 +137,23 @@ struct sunxi_ccm_reg {
> };
>
> /* apb2 bit field */
> -#define APB2_CLK_SRC_OSC24M 1
> -#define APB2_FACTOR_M 0
> -#define APB2_FACTOR_N 0
> +#define APB2_CLK_SRC_OSC24M (0x0<<24)
> +#define APB2_CLK_SRC_PLL6 (0x1<<24)
> +#define APB2_CLK_SRC_LOSC (0x2<<24)
> +#define APB2_CLK_SRC_MASK (0x3<<24)
Copy paste error, for sun6i this should be:
#define APB2_CLK_SRC_LOSC (0x0<<24)
#define APB2_CLK_SRC_OSC24M (0x1<<24)
#define APB2_CLK_SRC_PLL6 (0x2<<24)
#define APB2_CLK_SRC_MASK (0x3<<24)
Note that way APB2_CLK_SRC_OSC24M actually stays 1
instead of becoming 0 :)
> +#define APB2_CLK_RATE_N_1 (0x0<<16)
> +#define APB2_CLK_RATE_N_2 (0x1<<16)
> +#define APB2_CLK_RATE_N_4 (0x2<<16)
> +#define APB2_CLK_RATE_N_8 (0x3<<16)
> +#define APB2_CLK_RATE_N_MASK (3<<16)
> +#define APB2_CLK_RATE_M(m) (((m)-1)<<0)
> +#define APB2_CLK_RATE_M_MASK (0x1f<<0)
> +
> +/* apb2 gate field */
> +#define APB2_GATE_UART_SHIFT (16)
> +#define APB2_GATE_UART_MASK (0xff<<APB2_GATE_UART_SHIFT)
> +#define APB2_GATE_TWI_SHIFT (0)
> +#define APB2_GATE_TWI_MASK (0xf<<APB2_GATE_TWI_SHIFT)
>
> /* cpu_axi_cfg bits */
> #define AXI_DIV_SHIFT 0
> diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h
> b/arch/arm/include/asm/arch-sunxi/sys_proto.h
> index 61b29d8..c3e636e 100644
> --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
> +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
> @@ -11,7 +11,6 @@
>
> #include <linux/types.h>
>
> -void sr32(u32 *, u32, u32, u32);
> void sdelay(unsigned long);
>
> #endif
Otherwise this looks good.
Regards,
Hans
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