The original default may have been miscalculated as it was for 624MHz. The A23 user manual states that PLL6 should be fixed to 600MHz, and not any other rate.
Signed-off-by: Chen-Yu Tsai <[email protected]> --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index c524c29..1861673 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -172,7 +172,7 @@ struct sunxi_ccm_reg { #define PLL1_CFG_DEFAULT 0x90011b21 -#define PLL6_CFG_DEFAULT 0x90041911 +#define PLL6_CFG_DEFAULT 0x90041811 #define CCM_PLL6_CTRL_N_SHIFT 8 #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) -- 2.0.0.rc0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
