Requested by Marek as part of upstream review.
Signed-off-by: Ian Campbell <[email protected]>
---
board/sunxi/board.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/mmc/sunxi_mmc.c | 53 --------------------------------------------
2 files changed, 59 insertions(+), 53 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 82cead0..27feecc 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -23,6 +23,7 @@
#endif
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -66,10 +67,68 @@ int dram_init(void)
}
#ifdef CONFIG_GENERIC_MMC
+static void mmc_pinmux_setup(int sdc)
+{
+ unsigned int pin;
+
+ switch (sdc) {
+ case 0:
+ /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
+ for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ break;
+
+ case 1:
+#if CONFIG_MMC1_PG
+ /* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPG0_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#else
+ /* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
+ for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#endif
+ break;
+
+ case 2:
+ /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ break;
+
+ case 3:
+ /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
+ for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ break;
+
+ default:
+ printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
+ break;
+ }
+}
+
int board_mmc_init(bd_t *bis)
{
+ mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
+ mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
#endif
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 1fc2e49..b6a1b8a 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -14,7 +14,6 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
static void dumphex32(char *name, char *base, int len)
@@ -139,7 +138,6 @@ static int mmc_resource_init(int sdc_no)
static int mmc_clk_io_on(int sdc_no)
{
- unsigned int pin;
unsigned int pll_clk;
unsigned int divider;
struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
@@ -147,57 +145,6 @@ static int mmc_clk_io_on(int sdc_no)
debug("init mmc %d clock and io\n", sdc_no);
- /* config gpio */
- switch (sdc_no) {
- case 0:
- /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
- for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- break;
-
- case 1:
-#if CONFIG_MMC1_PG
- /* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
- for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN4I_GPG0_SDC1);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
-#else
- /* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
- for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
-#endif
- break;
-
- case 2:
- /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- break;
-
- case 3:
- /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
- for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- break;
-
- default:
- return -1;
- }
-
/* config ahb clock */
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
--
1.9.0
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
For more options, visit https://groups.google.com/d/optout.
