El 11/06/14 12:23, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 11:14 AM, Chen-Yu Tsai <w...@csie.org> wrote:
On Wed, Jun 11, 2014 at 11:11 PM, Emilio López <emi...@elopez.com.ar> wrote:
El 11/06/14 11:43, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 10:25 AM, Chen-Yu Tsai <w...@csie.org> wrote:
On Wed, Jun 11, 2014 at 10:23 PM, jonsm...@gmail.com <jonsm...@gmail.com>
wrote:
On Wed, Jun 11, 2014 at 10:17 AM, Chen-Yu Tsai <w...@csie.org> wrote:
On Wed, Jun 11, 2014 at 10:05 PM, jonsm...@gmail.com
<jonsm...@gmail.com> wrote:
Is there a DMAEngine implementation for the A20?
Audio drivers will want that.
Emilio (CC-ed) has been working on one, and he pushed out a branch I
think.
Depending on how much time it would take to implement the audio
drivers,
Audio support is fairly easy if DMAEngine is there and cyclic buffers
have been implemented.
Audio does need a DMA feature that not all DMA hardware implements. It
needs to be able to ask the DMA hardware what address (or how far
along) the transfer is currently at. That info is needed to implement
the mixer.
For example. You set audio up on a cyclic 16Kb DMA buffer playing
music. Now you want to make a beep that new email has arrived. The
audio system needs to be able to ask the DMA hardware where it is
inside that 16Kb buffer. Once it knows where the DMA pointer is, it
will mix that beep into music already existing in the buffer that
hasn't played yet.
Without this capability audio drivers will implement lots of little
chained buffers. Then as each one completes if knows where the DMA
pointer is. Finally there is code in ALSA that just guesses where the
DMA pointer is based on the system clock.
Does the A20 DMA hardware expose the current DMA pointer address in a
register?
There's a bit you can set on the configuration register so that the byte
counter register (pages 165, 170 on A20 user manual) returns the amount of
data left to transfer.
I think the default setting is to return the amount of data transferred.
Add that to the base pointer, and that should do it.
I have no idea about cyclic buffers though. Maybe it's just an implementation
issue?
Cyclic buffers are a power saving feature. There's no real need for
an interrupt at the end of the buffer just to reset the buffer pointer
to the beginning of the buffer. DMA hardware that implements cyclic
transfers will reset the pointer without interrupting.
It's not clear from the user manual, but sounds like the "continuous
mode" that the engine lets you enable.
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