ChenYu, are you going to add PLL2 clocks to your A23 support? Here's
my attempt so far at PLL2 support. I'm not sure if I got the
parenting support right.
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 263eb79..be643fc 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -91,6 +91,14 @@
clock-output-names = "pll1";
};
+ pll2: clk@01c20008 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-pll2-clk";
+ reg = <0x01c20008 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll2";
+ };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-pll4-clk";
@@ -327,6 +335,30 @@
clock-output-names = "ir1";
};
+ i2s0_clk: clk@01c200b8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-audio-clk";
+ reg = <0x01c200b8 0x4>;
+ clocks = <&pll2>;
+ clock-output-names = "i2s0";
+ };
+
+ ac97_clk: clk@01c200bc {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-audio-clk";
+ reg = <0x01c200bc 0x4>;
+ clocks = <&pll2>;
+ clock-output-names = "ac97";
+ };
+
+ spdif_clk: clk@01c200c0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-audio-clk";
+ reg = <0x01c200c0 0x4>;
+ clocks = <&pll2>;
+ clock-output-names = "spdif";
+ };
+
usb_clk: clk@01c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
@@ -344,6 +376,30 @@
clock-output-names = "spi3";
};
+ i2s1_clk: clk@01c200d8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-audio-clk";
+ reg = <0x01c200d8 0x4>;
+ clocks = <&pll2>;
+ clock-output-names = "i2s1";
+ };
+
+ i2s2_clk: clk@01c200dc {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-audio-clk";
+ reg = <0x01c200dc 0x4>;
+ clocks = <&pll2>;
+ clock-output-names = "i2s2";
+ };
+
+ codec_clk: clk@01c20140 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-codec-clk";
+ reg = <0x01c20140 0x4>;
+ clocks = <&pll2>;
+ clock-output-names = "codec";
+ };
+
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -807,6 +863,72 @@
clocks = <&osc24M>;
#pwm-cells = <3>;
};
+
+ spdif@01c21000 {
+ compatible = "allwinner,sun7i-a20-spdif";
+ reg = <0x01C21000 0x40>;
+ interrupts = <0 13 4>;
+ clocks = <&pll2>, <&apb0_gates 1>, <&spdif_clk>;
+ clock-names = "pll2", "apb", "spdif";
+ dmas = <&dma 0 2>, <&dma 0 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ac97@01c21400 {
+ compatible = "allwinner,sun7i-a20-ac97";
+ reg = <0x01C21400 0x40>;
+ interrupts = <0 14 4>;
+ clocks = <&pll2>, <&apb0_gates 2>, <&ac97_clk>;
+ clock-names = "pll2", "apb", "ac97";
+ dmas = <&dma 0 5>, <&dma 0 5>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s0: i2s@01c22000 {
+ compatible = "allwinner,sun7i-a20-i2s";
+ reg = <0x01C22000 0x40>;
+ interrupts = <0 16 4>;
+ clocks = <&pll2>, <&apb0_gates 3>, <&i2s0_clk>;
+ clock-names = "pll2", "apb", "i2s";
+ dmas = <&dma 0 3>, <&dma 0 3>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s1: i2s@01c22400 {
+ compatible = "allwinner,sun7i-a20-i2s";
+ reg = <0x01C22400 0x40>;
+ interrupts = <0 87 4>;
+ clocks = <&pll2>, <&apb0_gates 4>, <&i2s1_clk>;
+ clock-names = "pll2", "apb", "i2s";
+ dmas = <&dma 0 4>, <&dma 0 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s2: i2s@01c24400 {
+ compatible = "allwinner,sun7i-a20-i2s";
+ reg = <0x01C24400 0x40>;
+ interrupts = <0 90 4>;
+ clocks = <&pll2>, <&apb0_gates 8>, <&i2s2_clk>;
+ clock-names = "pll2", "apb", "i2s";
+ dmas = <&dma 0 6>, <&dma 0 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ codec: codec@01c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun7i-a20-codec";
+ reg = <0x01C22c00 0x40>;
+ interrupts = <0 30 4>;
+ clocks = <&pll2>, <&apb0_gates 0>, <&codec_clk>;
+ clock-names = "pll2", "apb", "codec";
+ dmas = <&dma 0 19>, <&dma 0 19>;
+ dma-names = "rx", "tx";
+ };
ir0: ir@01c21800 {
compatible = "allwinner,sun7i-a20-ir";
@@ -851,8 +973,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 16>;
- dmas = <&dma 0 8>, <&dma 0 8>;
- dma-names = "rx", "tx";
+ /*dmas = <&dma 0 8>, <&dma 0 8>;
+ dma-names = "rx", "tx"; */
status = "disabled";
};
@@ -1031,4 +1153,32 @@
interrupts = <1 9 0xf04>;
};
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&codec>;
+ master-clkdir-out;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ };
+ };
+
};
diff --git a/cop b/cop
new file mode 100755
index 0000000..727aee3
--- /dev/null
+++ b/cop
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+
+make zImage modules uImage dtbs
+cp /work/hans/sound/soc/sunxi/sunxi-codec.ko
/work/root/lib/modules/3.15.0+/kernel/sound/soc/sunxi
+
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 1d16c0c..b3483a7 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -212,6 +212,30 @@ static void sun8i_a23_get_pll1_factors(u32 *freq,
u32 parent_rate,
}
/**
+ * sun7i_get_pll2_factors()
+ * parent_rate is always 24Mhz
+ */
+
+static void sun7i_get_pll2_factors(u32 *freq, u32 parent_rate,
+ u8 *n, u8 *k, u8 *m, u8 *p)
+{
+ printk("JDS - sun7i_get_pll2_factors %d\n", *freq);
+ /* we were called to round the frequency, we can now return */
+ if (n == NULL)
+ return;
+
+ if (*freq == 22579200) {
+ *n = 79;
+ *m = 21; /* Pre */
+ *k = 4; /* Post */
+ } else {
+ *n = 86;
+ *m = 21; /* Pre */
+ *k = 4; /* Post */
+ }
+}
+
+/**
* sun4i_get_pll5_factors() - calculates n, k factors for PLL5
* PLL5 rate is calculated as follows
* rate = parent_rate * n * (k + 1)
@@ -482,6 +506,15 @@ static struct clk_factors_config sun8i_a23_pll1_config = {
.n_from_one = 1,
};
+static struct clk_factors_config sun7i_pll2_config = {
+ .nshift = 8,
+ .nwidth = 7,
+ .kshift = 26,
+ .kwidth = 4,
+ .mshift = 0,
+ .mwidth = 5,
+};
+
static struct clk_factors_config sun4i_pll5_config = {
.nshift = 8,
.nwidth = 5,
@@ -538,6 +571,12 @@ static const struct factors_data
sun8i_a23_pll1_data __initconst = {
.getter = sun8i_a23_get_pll1_factors,
};
+static const struct factors_data sun7i_a20_pll2_data __initconst = {
+ .enable = 31,
+ .table = &sun7i_pll2_config,
+ .getter = sun7i_get_pll2_factors,
+};
+
static const struct factors_data sun7i_a20_pll4_data __initconst = {
.enable = 31,
.table = &sun4i_pll5_config,
@@ -945,6 +984,10 @@ static const struct gates_data
sun6i_a31_usb_gates_data __initconst = {
.reset_mask = BIT(2) | BIT(1) | BIT(0),
};
+static const struct gates_data sunxi_codec_data __initconst = {
+ .mask = {BIT(31)},
+};
+
static void __init sunxi_gates_clk_setup(struct device_node *node,
struct gates_data *data)
{
@@ -1195,12 +1238,12 @@ free_clkdata:
}
-
/* Matches for factors clocks */
static const struct of_device_id clk_factors_match[] __initconst = {
{.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
{.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
+ {.compatible = "allwinner,sun7i-a20-pll2-clk", .data = &sun7i_a20_pll2_data,},
{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
{.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
@@ -1258,6 +1301,7 @@ static const struct of_device_id
clk_gates_match[] __initconst = {
{.compatible = "allwinner,sun4i-a10-usb-clk", .data =
&sun4i_a10_usb_gates_data,},
{.compatible = "allwinner,sun5i-a13-usb-clk", .data =
&sun5i_a13_usb_gates_data,},
{.compatible = "allwinner,sun6i-a31-usb-clk", .data =
&sun6i_a31_usb_gates_data,},
+ {.compatible = "allwinner,sunxi-codec-clk", .data = &sunxi_codec_data,},
{}
};
--
Jon Smirl
[email protected]
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
For more options, visit https://groups.google.com/d/optout.
