U-boot might have set up an fb which we, without dt, do not know how to
use. Just turn everything off and wait for a proper display driver to
kick in, or not.

Signed-off-by: Luc Verhaegen <[email protected]>
---
 arch/arm/plat-sunxi/core.c |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-sunxi/core.c b/arch/arm/plat-sunxi/core.c
index e7da395..63ef52d 100644
--- a/arch/arm/plat-sunxi/core.c
+++ b/arch/arm/plat-sunxi/core.c
@@ -388,8 +388,43 @@ struct sys_timer sw_sys_timer = {
        .init = sw_timer_init,
 };
 
+/*
+ * We might have a u-boot display driver, but we cannot access the framebuffer
+ * without dt, so we use this rather big hammer to shut down all engines until
+ * a proper graphics driver kicks in.
+ */
+static void
+sunxi_clk_graphics_shutdown(void)
+{
+#define SUNXI_CCMU_PLL3                0x010
+#define SUNXI_CCMU_PLL7                0x030
+#define SUNXI_CCMU_AHB_GATING1 0x064
+#define SUNXI_CCMU_DRAM_GATE   0x100
+       volatile unsigned int *ahb =
+               (void *) SW_VA_CCM_IO_BASE + SUNXI_CCMU_AHB_GATING1;
+       volatile unsigned int *dram =
+               (void *) SW_VA_CCM_IO_BASE + SUNXI_CCMU_DRAM_GATE;
+       volatile unsigned int *pll3 =
+               (void *) SW_VA_CCM_IO_BASE + SUNXI_CCMU_PLL3;
+       volatile unsigned int *pll7 =
+               (void *) SW_VA_CCM_IO_BASE + SUNXI_CCMU_PLL7;
+
+       /*
+        * Note that not all these bits apply for sun5i, as it has only one
+        * full set of display engines versus two on other SoCs. But since
+        * those bits are null anyway, there is no danger nulling them again.
+        */
+       *ahb &= ~0x0000F83C;
+       *dram &= ~0x0F000060;
+
+       /* These won't be used either. */
+       *pll3 &= ~0x80000000;
+       *pll7 &= ~0x80000000;
+}
+
 void __init sw_core_init(void)
 {
+       sunxi_clk_graphics_shutdown();
        sw_pdev_init();
 }
 
-- 
1.7.7

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