This is a purely mechanical conversion, replacing the ifdefs and preparing the code for the use of runtime Allwinner SoC type detection (within Allwinner A10/A13/A20 family).
Similar 'board_is_xxx()' calls are used for TI hardware. Signed-off-by: Siarhei Siamashka <[email protected]> --- arch/arm/cpu/armv7/sunxi/board.c | 52 +++++----- arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 7 +- arch/arm/cpu/armv7/sunxi/cpu_info.c | 36 ++++--- arch/arm/cpu/armv7/sunxi/dram.c | 171 +++++++++++++++++---------------- include/configs/sun4i.h | 2 + include/configs/sun5i.h | 2 + include/configs/sun7i.h | 2 + include/configs/sunxi-common.h | 12 +++ 8 files changed, 160 insertions(+), 124 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index f2cedbb..90e957c 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -50,22 +50,23 @@ u32 spl_boot_mode(void) int gpio_init(void) { -#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) - sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); - sunxi_gpio_set_pull(SUNXI_GPB(23), 1); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); - sunxi_gpio_set_pull(SUNXI_GPB(20), 1); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); - sunxi_gpio_set_pull(SUNXI_GPG(4), 1); -#else -#error Unsupported console port number. Please fix pin mux settings in board.c -#endif - + if (CONFIG_CONS_INDEX == 1 && (SOC_IS_SUN4I() || SOC_IS_SUN7I())) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(23), 1); + } else if (CONFIG_CONS_INDEX == 1 && SOC_IS_SUN5I()) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(20), 1); + } else if (CONFIG_CONS_INDEX == 2 && SOC_IS_SUN5I()) { + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); + sunxi_gpio_set_pull(SUNXI_GPG(4), 1); + } else { + /* Unsupported console port number. + * Please fix pin mux settings in board.c */ + hang(); + } return 0; } @@ -87,12 +88,19 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I) - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n"); +#if !defined CONFIG_SPL_BUILD + int soc_is_sun6i = 0; +#ifdef CONFIG_SUN6I + soc_is_sun6i = 1; +#endif + if (SOC_IS_SUN7I() || soc_is_sun6i) { + /* Enable SMP mode for CPU0, by setting bit 6 of + * Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #1 << 6\n" + "mcr p15, 0, r0, c1, c0, 1\n" : : : "r0"); + } #endif clock_init(); diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index ecbdb01..1af285e 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -35,9 +35,10 @@ void clock_init_safe(void) APB0_DIV_1 << APB0_DIV_SHIFT | CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); -#ifdef CONFIG_SUN7I - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); -#endif + + if (SOC_IS_SUN7I()) + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); #ifdef CONFIG_SUNXI_AHCI setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 5cf35ac..1134b21 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -13,22 +13,28 @@ #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { -#ifdef CONFIG_SUN4I - puts("CPU: Allwinner A10 (SUN4I)\n"); -#elif defined CONFIG_SUN5I - u32 val = readl(SUNXI_SID_BASE + 0x08); - switch ((val >> 12) & 0xf) { - case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break; - case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break; - case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; - default: puts("CPU: Allwinner A1X (SUN5I)\n"); + if (SOC_IS_SUN4I()) { + puts("CPU: Allwinner A10 (SUN4I)\n"); + } else if (SOC_IS_SUN5I()) { + u32 val = readl(SUNXI_SID_BASE + 0x08); + switch ((val >> 12) & 0xf) { + case 0: + puts("CPU: Allwinner A12 (SUN5I)\n"); + break; + case 3: + puts("CPU: Allwinner A13 (SUN5I)\n"); + break; + case 7: + puts("CPU: Allwinner A10s (SUN5I)\n"); + break; + default: + puts("CPU: Allwinner A1X (SUN5I)\n"); + } + } else if (SOC_IS_SUN7I()) { + puts("CPU: Allwinner A20 (SUN7I)\n"); + } else { + puts("CPU: SUNXI Family\n"); } -#elif defined CONFIG_SUN7I - puts("CPU: Allwinner A20 (SUN7I)\n"); -#else -#warning Please update cpu_info.c with correct CPU information - puts("CPU: SUNXI Family\n"); -#endif return 0; } #endif diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index 584f742..05cd66f 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -74,22 +74,23 @@ static void mctl_ddr3_reset(void) struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; -#ifdef CONFIG_SUN4I struct sunxi_timer_reg *timer = (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; u32 reg_val; - - writel(0, &timer->cpu_cfg); - reg_val = readl(&timer->cpu_cfg); - - if ((reg_val & CPU_CFG_CHIP_VER_MASK) != - CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) { - setbits_le32(&dram->mcr, DRAM_MCR_RESET); - udelay(200); - clrbits_le32(&dram->mcr, DRAM_MCR_RESET); - } else -#endif - { + int reset_done = 0; + + if (SOC_IS_SUN4I()) { + writel(0, &timer->cpu_cfg); + reg_val = readl(&timer->cpu_cfg); + if ((reg_val & CPU_CFG_CHIP_VER_MASK) != + CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) { + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(200); + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + reset_done = 1; + } + } + if (!reset_done) { clrbits_le32(&dram->mcr, DRAM_MCR_RESET); udelay(200); setbits_le32(&dram->mcr, DRAM_MCR_RESET); @@ -112,14 +113,10 @@ static void mctl_ddr3_reset(void) static void mctl_set_drive(void) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - -#ifdef CONFIG_SUN7I - clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), -#else - clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), -#endif - DRAM_MCR_MODE_EN(0x3) | - 0xffc); + clrsetbits_le32(&dram->mcr, + DRAM_MCR_MODE_NORM(0x3) | + (SOC_IS_SUN7I() ? (0x3 << 28) : 0), + DRAM_MCR_MODE_EN(0x3) | 0xffc); } static void mctl_itm_disable(void) @@ -201,8 +198,7 @@ static void mctl_enable_dllx(u32 phase) udelay(22); } -static u32 hpcr_value[32] = { -#ifdef CONFIG_SUN5I +static u32 hpcr_value_sun5i[32] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -211,8 +207,9 @@ static u32 hpcr_value[32] = { 0x1035, 0x0731, 0x1031, 0, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0 -#endif -#ifdef CONFIG_SUN4I +}; + +static u32 hpcr_value_sun4i[32] = { 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0, 0, 0, 0, 0, 0, @@ -221,8 +218,9 @@ static u32 hpcr_value[32] = { 0x1035, 0x0731, 0x1031, 0x0735, 0x1035, 0x1031, 0x0731, 0x1035, 0x1031, 0x0301, 0x0301, 0x0731 -#endif -#ifdef CONFIG_SUN7I +}; + +static u32 hpcr_value_sun7i[32] = { 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0, 0, 0, 0, @@ -236,13 +234,21 @@ static u32 hpcr_value[32] = { * but boot0 code skips #28 and #30, and sets #29 and #31 to the * value from #28 entry (0x1031) */ -#endif }; static void mctl_configure_hostport(void) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; u32 i; + u32 *hpcr_value; + if (SOC_IS_SUN4I()) + hpcr_value = hpcr_value_sun4i; + else if (SOC_IS_SUN5I()) + hpcr_value = hpcr_value_sun5i; + else if (SOC_IS_SUN7I()) + hpcr_value = hpcr_value_sun7i; + else + panic("Can't detect the SoC type"); for (i = 0; i < 32; i++) writel(hpcr_value[i], &dram->hpcr[i]); @@ -258,9 +264,8 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) u32 pll6x_clk = clock_get_pll6() / 1000000; u32 pll5p_clk = clk / 24 * 48; u32 pll5p_rate, pll6x_rate; -#ifdef CONFIG_SUN7I - pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ -#endif + if (SOC_IS_SUN7I()) + pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ /* setup DRAM PLL */ reg_val = readl(&ccm->pll5_cfg); @@ -311,13 +316,14 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) - /* reset GPS */ - clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); - setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); - udelay(1); - clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); -#endif + if (SOC_IS_SUN4I() || SOC_IS_SUN7I()) { + /* reset GPS */ + clrbits_le32(&ccm->gps_clk_cfg, + CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); + udelay(1); + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); + } /* setup MBUS clock */ if (!mbus_clk) @@ -348,19 +354,15 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) * open DRAMC AHB & DLL register clock * close it first */ -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) - clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); -#else - clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); -#endif + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | + ((SOC_IS_SUN5I() || SOC_IS_SUN7I()) ? CCM_AHB_GATE_DLL : 0)); + udelay(22); /* then open it */ -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) - setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); -#else - setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); -#endif + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | + ((SOC_IS_SUN5I() || SOC_IS_SUN7I()) ? CCM_AHB_GATE_DLL : 0)); + udelay(22); } @@ -417,21 +419,23 @@ static int dramc_scan_readpipe(void) static void dramc_clock_output_en(u32 on) { -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - - if (on) - setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); - else - clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); -#endif -#ifdef CONFIG_SUN4I struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (on) - setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); - else - clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); -#endif + + if (SOC_IS_SUN5I() || SOC_IS_SUN7I()) { + if (on) + setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); + else + clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); + } + if (SOC_IS_SUN4I()) { + if (on) + setbits_le32(&ccm->dram_clk_cfg, + CCM_DRAM_CTRL_DCLK_OUT); + else + clrbits_le32(&ccm->dram_clk_cfg, + CCM_DRAM_CTRL_DCLK_OUT); + } } /* tRFC in nanoseconds for different densities (from the DDR3 spec) */ @@ -527,27 +531,25 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) u32 reg_val; u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF; -#ifndef CONFIG_SUN7I /* Appears that some kind of automatically initiated default * ZQ calibration is already in progress at this point on sun4i/sun5i * hardware, but not on sun7i. So it is reasonable to wait for its * completion before doing anything else. */ - await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE); -#endif + if (!SOC_IS_SUN7I()) + await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE); /* ZQ calibration is not really useful unless ODT is enabled */ if (!odt_en) return; -#ifdef CONFIG_SUN7I /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock * unless bit 24 is set in SDR_ZQCR1. Not much is known about the * SDR_ZQCR1 register, but there are hints indicating that it might * be related to periodic impedance re-calibration. This particular * magic value is borrowed from the Allwinner boot0 bootloader, and * using it helps to avoid troubles */ - writel((1 << 24) | (1 << 1), &dram->zqcr1); -#endif + if (SOC_IS_SUN7I()) + writel((1 << 24) | (1 << 1), &dram->zqcr1); /* Needed at least for sun5i, because it does not self clear there */ clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); @@ -597,10 +599,10 @@ static unsigned long dramc_init_helper(struct dram_para *para) /* dram clock off */ dramc_clock_output_en(0); -#ifdef CONFIG_SUN4I - /* select dram controller 1 */ - writel(DRAM_CSEL_MAGIC, &dram->csel); -#endif + if (SOC_IS_SUN4I()) { + /* select dram controller 1 */ + writel(DRAM_CSEL_MAGIC, &dram->csel); + } mctl_itm_disable(); mctl_enable_dll0(para->tpr3); @@ -654,9 +656,8 @@ static unsigned long dramc_init_helper(struct dram_para *para) writel(para->tpr2, &dram->tpr2); reg_val = DRAM_MR_BURST_LENGTH(0x0); -#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)) - reg_val |= DRAM_MR_POWER_DOWN; -#endif + if (SOC_IS_SUN5I() || SOC_IS_SUN7I()) + reg_val |= DRAM_MR_POWER_DOWN; reg_val |= DRAM_MR_CAS_LAT(para->cas - 4); reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock)); writel(reg_val, &dram->mr); @@ -668,11 +669,10 @@ static unsigned long dramc_init_helper(struct dram_para *para) /* disable drift compensation and set passive DQS window mode */ clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); -#ifdef CONFIG_SUN7I /* Command rate timing mode 2T & 1T */ - if (para->tpr4 & 0x1) + if (SOC_IS_SUN7I() && (para->tpr4 & 0x1)) setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); -#endif + /* initialize external DRAM */ mctl_ddr3_initialize(); @@ -718,13 +718,16 @@ unsigned long dramc_init(struct dram_para *para) /* try to autodetect the DRAM bus width and density */ para->io_width = 16; para->bus_width = 32; -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) - /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */ - para->density = 4096; -#else - /* all A0-A15 address lines on A20, which allow density 8192 */ - para->density = 8192; -#endif + + if (SOC_IS_SUN4I() || SOC_IS_SUN5I()) { + /* only A0-A14 address lines on A10/A13, + * limiting max density to 4096 */ + para->density = 4096; + } else { + /* all A0-A15 address lines on A20, + * which allow density 8192 */ + para->density = 8192; + } dram_size = dramc_init_helper(para); if (!dram_size) { diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 5611ecc..d08804c 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -14,6 +14,8 @@ #define CONFIG_SUN4I /* sun4i SoC generation */ #define CONFIG_CLK_FULL_SPEED 1008000000 +#define SOC_IS_SUN4I() 1 + #define CONFIG_SYS_PROMPT "sun4i# " #ifdef CONFIG_USB_EHCI diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index 6066371..b6c0669 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -14,6 +14,8 @@ #define CONFIG_SUN5I /* sun5i SoC generation */ #define CONFIG_CLK_FULL_SPEED 1008000000 +#define SOC_IS_SUN5I() 1 + #define CONFIG_SYS_PROMPT "sun5i# " #ifdef CONFIG_USB_EHCI diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index a902b84..d3f0322 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -15,6 +15,8 @@ #define CONFIG_SUN7I /* sun7i SoC generation */ #define CONFIG_CLK_FULL_SPEED 912000000 +#define SOC_IS_SUN7I() 1 + #define CONFIG_SYS_PROMPT "sun7i# " #ifdef CONFIG_USB_EHCI diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 6a3044f..267bf2a 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -13,6 +13,18 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H +#ifndef SOC_IS_SUN4I +#define SOC_IS_SUN4I() 0 +#endif + +#ifndef SOC_IS_SUN5I +#define SOC_IS_SUN5I() 0 +#endif + +#ifndef SOC_IS_SUN7I +#define SOC_IS_SUN7I() 0 +#endif + /* * High Level Configuration Options */ -- 1.8.3.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. 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