On 17/08/14 21:18, jonsm...@gmail.com wrote: > I think I found the bug, my sgtl5000 is happy now at lower clock > speeds. I was missing a 'L' and a value got truncated to 32 bits.
Sorry for the late reply, I guess we're in different timezones :) Yes, that seems to work here too, giving expected outputs at lower frequencies. Noticeable that at higher frequencies there are large jumps, for example it gets to 6MHz then jumps to 8MHz then to 24MHz period values to frequencies look like this up to 83 24MHz 84 - 104 8MHz 105 - 145 6MHz 146 - 187 4.8MHz 188 - 229 4MHz 230 - 270 3.4MHz 271 - 312 3MHz and carries on in similar fashion with the jumps becoming smaller each time as frequency decreases. I didn't look at the code in detail, but presumably this is just a an expected result of which prescaler and divisor are being picked and the PWM not really being intended to be used at high frequencies. It gets much less noticable as you go below 1MHz. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
