On Thu, Aug 14, 2014 at 10:22:04PM +0200, Luc Verhaegen wrote: > On Thu, Aug 14, 2014 at 09:47:34PM +0200, Luc Verhaegen wrote: > > > > > 4) Working on 3). made me realize that the clk setup code tries to use m > > > = 16 which > > > won't work. > > > > Hrm, that i need to go verify, as i am definitely doing that in my KMS > > code as well. Nice catch. > > code: > sunxi_io_mask(ccmu, SUNXI_LCDC0_CH1_CLK, best_m - 1, 0x0F); > > According to the datasheet: > LCDx_CH1 bits 3:0: m - 1, the divider is from 1 - 16. > > I thought i tested this quite extensively, i am the only one in the > business who has tested dotclocks extensively (cfr unichrome or > radeonhd code), so i wouldn't let that slide. > > I will go verify this though. If m=16 is possible, i will add a comment > to avoid future confusion. > > Luc Verhaegen.
I just had KMS set me Modeline 14:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 on VGA. lcdc_pll_calculate: 040000kHz = 040000kHz: (2 * 3MHz * 100) / 15 Which showed me the correct 60Hz and 37.9kHz. I then manually changed the divider to 16, by changing the value from 0x8200800E to 0x8200800F And my test CRT now claims to 56Hz and 35.5kHz, right on the money. So 16 is a perfectly valid value for that calculation, i will adjust the comment accordingly. My test CRT is refusing to show 640x480 though, so while i diligently tested through the edges of the ranges (both of the internal loop, as of the external divider), i did mess something else up :) Ooh, that poor monitor, will it survive its 13th year? ;) Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
