Hi, In attempt to understand how to set the A31 core freq. I think I need to understand how to set the PLL1 tuning reg (hw addr: 0x01c20250) as changing only the PLL1's freq. (0x01c20000) is not enough.
I could not find any info. about this reg in the various linux SDK available and the only thing I could infer from the A20 chip is that its LS bits are define the "WaveBottom" - does anyone know what that is? Thanks -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
