How do you interpret this? 1.12. DMA 1.12.1. Overview
There are two kinds of DMA in the chip. One is Normal DMA with 8 channels, the other is Dedicated DMA with 8 channels . For normal DMA, only one channel can be active and the sequence is in line with the priority level. While for the dedicated DMA, at most 8-channel can be active at the same time if their source or destination has no conflict. The dedicated DMA can only transfer data between the DRAM and the module. ------------------------------------ Emilio interpreted it to mean that we can't turn on two normal DMA transfers at the same time. That's a real mess if one of those transfers sits around waiting for a couple seconds to fulfill the request. ALSA could write 256K to the I2S buffer which would take 1.5 seconds to slowly spool out to the audio hardware. But this doesn't make sense on normal DMA, what is the point of making eight sets of normal DMA registers if only one can be active? Why can't I have two DMA requests setup and waiting for data to arrive? This might mean that if one of the eight normal channels asserts DRQ it will only service that DRQ until it deasserts. In other words it won't service multiple active DRQs and round robin between them. That makes more sense - there is only one set of transfer hardware in the normal DMA engine. Each dedicated DMA has its own transfer hardware. It should be legal to have two cyclic requests sitting there, and then it makes sense that only one of the two can be actively moving data. The FIFOs will mask this. So how does this hardware work? -- Jon Smirl [email protected] -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
