The Allwinner SoCs that have an HDMI pin, also have a memory-mapped
HDMI-CEC register located at HDMI base 0xf1c16000 plus the offset 0x214.
This register provides the following bits

#define CEC_RX     0x0100  /* phys. line value, either high or low */
#define CEC_TX     0x0200
#define CEC_ENABLE 0x0800

Other bits are unused.

I asked Allwinner about CEC once but they only replied that A10s doesn't
have a hardware CEC core.

You can find examples of using the CEC register in some unfinished CEC code
in the 3.4 linux-sunxi kernel.

--Vladimir


On 3 October 2014 07:33, Chen-Yu Tsai <[email protected]> wrote:

> Hi,
>
> On Fri, Oct 3, 2014 at 3:29 AM, [email protected] <[email protected]>
> wrote:
> > I
> >
> > On Thu, Oct 2, 2014 at 1:19 PM, Christian Ege <[email protected]> wrote:
> >> During a quick search I had not been able to find any HDMI CEC driver.
> In
> >> the docs available there is only one Register about CEC.
> >>
> >> I thought about implementation of an driver and libcec support for the
> A20.
> >
> > I believe CEC is just I2C on the HDMI connector.
> >
> > So maybe --- it is one of the I2C devices. Then that bit enables it
> > onto the HDMI pin? Just a guess.
> >
> > EDID works the same way. How is it implemented?
>
> You are referring to DDC. The HDMI block has a separate DDC controller.
> IIRC, the DDC pins also have standard TWI muxed on them, so you could
> use either one.
>
> But this is entirely irrelevant to the original question.
>
> As Christian stated, the HDMI block does have a register named
> HDMI_HDP_CEC. However it does not contain any useful descriptions.
> Also the SoC does have a pin for HDMI CEC.
>
> Best ask Allwinner for some help.
>
>
> ChenYu
>
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