Omg, you are really know to less of hardware.

RXC+/- === Clkin+/-
VSS=GND=ground
VCC=VDD=3.3V power supply

2014-10-11 14:43 GMT+08:00 đeli hađiselimović <[email protected]>:
> Yeah I got that, but I still dont know which one is the Clkin+/-, ground and
> VDD..
>
>
> Dana subota, 11. listopada 2014. 02:56:05 UTC+2, korisnik Jhon Yi napisao
> je:
>>
>> Maybe you should take a little more time to read the guides.
>>
>> ///////////////////////////////////////
>> LCD interface define what type of interface to use for LCD. For LVDS
>> the right value is 3:
>>
>>  ; lcd interface
>>  lcd_if = 3
>>
>> Check whether 24 or 18 bit color is used, and set
>>
>>  lcd_lvds_bitwidth = 1 (if 18bit (RGB666) is used)
>>
>> RX0+ = LCD0-D0
>> RX0- = LCD0-D1
>> RX1+ = LCD0-D3
>> RX1- = LCD0-D4
>> RX2+ = LCD0-D5
>> RX2- = LCD0-D6
>> RXC+ = LCD0-D7
>> RXC- = LCD0-D8
>>
>> You could ignore EDID pins:
>> 4        V EEDID    DDC 3.3V power
>> 5        NC         Reserved for supplier test point
>> 6        Clk EEDID  DDC Clock
>> 7        DATA EEDID DDC Data
>>
>>
>>
>>
>> 2014-10-10 15:07 GMT+08:00 đeli hađiselimović <[email protected]>:
>> > Hi!
>> >
>> > I found out the LCD_CON on OLinuxino-micro A20 could output LVDS instead
>> > of
>> > TTL which is default if I get it right.
>> >
>> > Now I checked the FEX guide
>> >
>> > http://linux-sunxi.org/Fex_Guide#lcd.5B0.2F1.5D_configuration
>> >
>> > and this example
>> >
>> > http://linux-sunxi.org/Cubieboard/LVDS
>> >
>> >
>> > I dont see from here how to activate ports on A20 (for example PD00 -
>> > PD18)
>> > to represent the 19 pins required to drive the TFT-LCD.
>> >
>> > My panel is QD15TL0206 and its pinout:
>> >
>> > Interface Cable Pin Assignments
>> > PIN NO . SYMBOL     FUNCTION
>> >
>> > 1        VSS        Ground
>> > 2        VDD        Power Supply, 3.3 V (typical)
>> > 3        VDD        Power Supply, 3.3 V (typical)
>> > 4        V EEDID    DDC 3.3V power
>> > 5        NC         Reserved for supplier test point
>> > 6        Clk EEDID  DDC Clock
>> > 7        DATA EEDID DDC Data
>> > 8        Rin0-      - LVDS differential data input (R0-R5, G0) (odd
>> > pixels)
>> > 9        Rin0+      + LVDS differential data input (R0-R5, G0) (odd
>> > pixels)
>> > 10       VSS        Ground
>> > 11       Rin1-      - LVDS differential data input (G1-G5, B0-B1) (odd
>> > pixels)
>> > 12       Rin1+      + LVDS differential data input (G1-G5, B0-B1) (odd
>> > pixels)
>> > 13       VSS        Ground
>> > 14       Rin2-      - LVDS differential data input (B2-B5, HS, VS, DE)
>> > (odd
>> > pixels)
>> > 15       Rin2+      + LVDS differential data input (B2-B5, HS, VS, DE)
>> > (odd
>> > pixels)
>> > 16       VSS        Ground
>> > 17       ClkIN-     - LVDS differential clock input (odd pixels)
>> > 18       ClkIN+     + LVDS differential clock input (odd pixels)
>> > 19       VSS        Ground
>> >
>> > Cheers,
>> >
>> > Miha
>> >
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