Hi everyone,
the boot log shows a very unhappy nand driver.
--
[ 0.682894] Division by zero in kernel.
[ 0.689714] [<c001540c>] (unwind_backtrace+0x0/0x12c) from [<c03d41f8>]
(Ldiv0+0x8/0x10)
[ 0.696123] [<c03d41f8>] (Ldiv0+0x8/0x10) from [<c047351c>]
(get_cmu_clk+0x30/0x40)
[ 0.703360] [<c047351c>] (get_cmu_clk+0x30/0x40) from [<c047354c>]
(set_nand_clock+0x20/0x80)
[ 0.710497] [<c047354c>] (set_nand_clock+0x20/0x80) from [<c09b2bb4>]
(nand_init+0x68/0x1c4)
[ 0.717906] [<c09b2bb4>] (nand_init+0x68/0x1c4) from [<c0008698>]
(do_one_initcall+0x114/0x16c)
[ 0.725577] [<c0008698>] (do_one_initcall+0x114/0x16c) from [<c09979f8>]
(kernel_init+0x190/0x228)
[ 0.733160] [<c09979f8>] (kernel_init+0x190/0x228) from [<c000f7ec>]
(kernel_thread_exit+0x0/0x8)
[ 0.736507] [NAND] nand driver version: 0x2 0x9
[ 0.742146] [SCAN_ERR] search nand physical architecture parameter failed!
[ 0.744506] [NAND]init_blklayer fail
--
Apparently, this happens in drivers/block/sunxi_nand/nfd/nand_blk.c:1107
--
#ifndef USE_SYS_CLK
__u32 get_cmu_clk(void)
{
__u32 reg_val;
__u32 div_p, factor_n;
__u32 factor_k, factor_m;
__u32 clock;
reg_val = *(volatile unsigned int *)(0xf1c20000 + 0x20);
div_p = (reg_val >> 16) & 0x3;
factor_n = (reg_val >> 8) & 0x1f;
factor_k = ((reg_val >> 4) & 0x3) + 1;
factor_m = ((reg_val >> 0) & 0x3) + 1;
clock = 24 * factor_n * factor_k/div_p/factor_m;
return clock;
}
--
>From this code, since factor_m > 0, it is div_p being zero.
The related Android log lines are:
--
<4>[ 1.651812] nand_init,line:1400
<4>[ 1.651837] [NAND]nand driver, init.
<4>[ 1.651852] [NAND] nand driver(A20) version: 0x2, 0x12, data: 20130627
1522
<4>[ 1.651863] [NAND] nand clk request start
<4>[ 1.651898] [NAND] nand clk request ok!
<4>[ 1.651999] [NAND DMA] request dma success
<4>[ 1.652011] [NAND DMA] set fulldone_cb success
<4>[ 1.652410] nand interrupt register ok
<4>[ 1.652426] [NAND] get nand_good_block_ratio from script: 870
<4>[ 1.652506] [NAND DMA] start dma*****************************************
--
Since the driver mentions explicitly '(A20)', I might be running
an unsuited driver. Is this a known A20 issue or particular to
my installation? Instead using CONFIG_NAND, should I better
give CONFIG_NAND_TEST a shot?
The A20 handbook does not mention the register, but
./arch/arm/plat-sunxi/include/plat/platform.h:182 has a
#define SW_VA_CCM_IO_BASE 0xf1c20000,
and finally relates to CCM_PLL5_CFG this via
http://linux-sunxi.org/Clock_Control_Module#Timer_Registers
where it is cited as being A10 material.
But even if it is A10-only material, something appears to be fishy
either the code or the wiki page:
| CCM_PLL5_P 16:17 Read/Write 0x00
| 0x00 = 1
| 0x01 = 2
| 0x02 = 3
| 0x03 = 4
| PLL5 external factor P
Here, 0x00 is perfectly legal and the above code should read IMO
| div_p = ((reg_val >> 16) & 0x3) + 1;
But perhaps I'm reading this wrong.
Kind regards,
Lars
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