Hi,
On 02/24/2015 08:04 PM, Siarhei Siamashka wrote:
On Tue, 24 Feb 2015 18:11:22 +0100
Hans de Goede <[email protected]> wrote:
Hi,
On 02/24/2015 03:18 AM, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start. And if L2EN is not set,
then the Linux system ends up booted with the L2 cache disabled.
According to the Cortex-A8 TRM, the L2 cache is only enabled when
both L2EN bit and the C bit from the CP15 Control Register c1 are
set. Because the BROM does not set the C bit, this change should
not affect the functionality of the FEL mode in any way.
Signed-off-by: Siarhei Siamashka <[email protected]>
Wouldn't it be better to do this in u-boot ?
Yes, it was originally a patch for u-boot.
But now I'm not so sure. The 'fel' tool tries to abstract this stuff
and make the SPL uploaded via FEL look functionally equivalent to
loading it from an SD card (except for patching the "eGON.BT0"
signature in memory and also using some areas in SRAM outside
the first 32 KiB).
The L2EN bit setup differs for the SD card boot and the FEL mode cases.
So the 'fel' tool tries to correct this defect. Just because it can.
Ah yes I see this a FEL only thing, so yes lets do this in the fel tool
then:
Acked-by: Hans de Goede <[email protected]>
Regards,
Hans
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