Hello,
I am using Banana PI board (on A20), and GNU / Linux.
I have tried to work with the UART at high speed. When work at a baudrate
<= 115200 all is fine. If use uart baudrate 230400, 460800 and more data
damage while transferring.
I think it may be caused by incorrect configuration UART_CLK. UART_CLK
depends on APB1.
The default source frequency for APB1 is OSC24M. So the default frequency
APB1 = 24 MHz. For 115200 tolerance = 0.16026%, and for the 230400 -
8.5069%. It is too high, i think. And that's why errors occur during
transfer.
To solve the problem, I think it is possible to increase APB1 frequency up
to 96 MHz. This will give an acceptable tolerance up to 460800 baudrate. To
do this, I have modified clock.c: added APB1 frequency in script.bin (see
attach). I also added value apb1 = 96 in script.bin.
After this patch APB1 frequency installed correctly (i've seen debug
message during boot). But bytes damaged while transfer at any speed.
Maybe you can help me? What i've left out?
Thanks in advance.
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diff --git a/arch/arm/mach-sun7i/clock/clock.c b/arch/arm/mach-sun7i/clock/clock.c
index 26fe462..36e08aa 100644
--- a/arch/arm/mach-sun7i/clock/clock.c
+++ b/arch/arm/mach-sun7i/clock/clock.c
@@ -126,6 +126,24 @@ int clk_init(void)
}
}
+ if (script_parser_fetch("clock", "apb1", &val, sizeof(int)) == 0) {
+ struct clk *tmpClk;
+ __u32 tmpRate, min, max;
+ CCU_INF("script config apb1 to %dMHz\n", val);
+ clk = &aw_clock[AW_SYS_CLK_APB1];
+ tmpClk = &aw_clock[AW_SYS_CLK_PLL62];
+ clk_set_parent(clk, tmpClk);
+ tmpRate = clk_get_rate(tmpClk) / 1000000;
+ min = (tmpRate / (8 * 32));
+ max = tmpRate;
+ if (val >= min && val <= max) {
+ clk_enable(clk);
+ clk_set_rate(clk, val * 1000000);
+ } else {
+ CCU_ERR(" invalid value, must in %dMHz ~ %dGHz\n", min, max);
+ }
+ }
+
return 0;
}
arch_initcall(clk_init);
