On Monday, August 31, 2015 at 9:38:29 PM UTC+2, CodeKipper wrote: > > On 31 August 2015 at 08:31, Andrea Venturi <[email protected] > <javascript:>> wrote: > > > > > > Il giorno domenica 30 agosto 2015 13:55:14 UTC+2, Alexis Jeandet ha > scritto: > >> > >> Hi Andrea, > >> > >> Indeed my song is mono, so that may explain the issue. > >> > > > > ok > > > >> > >> I also continued to investigate the code from Marcus, which if I > >> understood correctly, is based on your code. I got some successful > results > >> also with this code. I think that Marcus wanted to merge the two > structures > >> sunxi_priv and sunxi_i2s_info and remove the sunxi_iis instance. > > > > > > > > yes; the sunxi_iis is a leftover of the original legacy AW driver and > the > > useful fields should be folded into the "private" data structure of the > > relevant alsa module. > > > >> > >> There is still some points I don't get yet, if I understand correctly > the > >> UDA is supposed to generate the sysclock with it's own PLL from bclk? > > > Hi All, > I've now joined the working i2s club...managed to get my uda1380 > singing but there are a few quirks that I will need to look at. For > example my audio test file of choice doesn't output audio(it's > 44.1KHz) and skips through the file quickly. If I play a 48KHz file I > get audio and then if I go back to the original audio file then it > works. It looks like none of the clock divisors are being set up > correctly..and I will check the logs tomorrow. I've also been able to > play 192KHz files but then if I play them again then it plays slow. > BR, > CK > I saw this behaviour also, If you play 3 time the same file it will also work. First I thought it may come from the uda driver because of i2c registers cache but it seems ok. It looks like a problem with the order the things are done, maybe some register should be set in a different order on i2s side? In more elaborated datasheet you usually get some procedure to initialise the device and to configure it.
> > > > IIRC it's a PLL from the "left right" clock (ie frame rate 44.1 or 48 > KHz) > > and the proper UDA register is set when there's WSPLL=1 on device tree.. > > > >> > >> Then you have to set the multiplication factor on the UDA? For each > song? > > > > > > for earch sample rate.. > > > >> > >> Or you just set it to 256 or 128fs and then just focus on i2s > interface? > >> In this case 24 bits resolution wouldn't be possible? > > > > > > the bit clock is a multiple of the FS changing when you have different > bit > > resolutions. > > > >> > >> Don't understand yet what ALSA does exactly, and I didn't check what is > >> done on i2c side. > >> > >> Best regards, > >> Alexis. > > > > -- > > You received this message because you are subscribed to the Google > Groups > > "linux-sunxi" group. > > To unsubscribe from this group and stop receiving emails from it, send > an > > email to [email protected] <javascript:>. > > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
