On Wed, 23 Sep 2015 01:25:01 -0700 (PDT) tandresen1...@gmail.com wrote: > Am Sonntag, 20. September 2015 11:14:29 UTC+2 schrieb tandre...@gmail.com: > > > > Hi, > > > > does anyone know the "right" voltage settings for A20-SOM modules or can > > someone > > explain why the seetings in u-boot as they are? > > > > The fex script of the official Olimex images contain following settings: > > > > boot_clock = 912 > > dcdc2_vol = 1450 > > dcdc3_vol = 1300 > > ldo2_vol = 3000 > > ldo3_vol = 2800 > > ldo4_vol = 2800 > > power_start = 1 > > storage_type = 0 > > > > These settings are different to the settings in recent u-boot versions. > > > > The dcdc2_vol is above the maximum of 1.4 V - in u-boot it s set to 1.4V > > which seems to right imho. > > But why is dcd3_vol set to 1.25 V in u-boot and not to 1.3V?
> thanks for these information. > > But most if the things stated in these threads are about overclocking. Why do you get this idea? http://linux-sunxi.org/Hardware_Reliability_Tests page is NOT about overclocking. It is about ensuring that the CPU and DRAM voltage/frequency/timings/impedance/... settings are reliable. Which is not always the case at least with the mainline U-Boot. Regardless of the declared priorities, the reliability is not handled properly in practice and this is a systematic issue. > I think running the A20-SOM at 912 MHz and a DRAM clock of 384 is definitly > not overclocking. What kind of A20-SOM are you talking about? There is only "A20-Olimex-SOM-EVB" supported in the mainline U-Boot: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=50222f3bab2213fa440712d2f46ae7f9314f3b7a And as you can see, it currently uses the CONFIG_DRAM_CLK=480 setup. Then we have dcdc2 and dcdc3 settings, which differ from what was selected by OLIMEX. Using different settings is not necessarily bad, but this normally needs a proper justification. Regarding 480MHz DRAM clock speed in OLIMEX boards. There was and still is some controversy about it: https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg10085.html "BTW, the blog post https://olimex.wordpress.com/2014/10/27/a20-olinuxino-lime2-review-and-updates/ says that "Much better routing of DDR3 memory. We increased the number of layers to 8 vs the 6 layers in LIME, we put the DDR3 memory closer to the A20, we layout the tracks shorter, as result now LIME2 runs with DDR3 on 532Mhz on LIME there were problems to run DDR3 at more than 400Mhz" I'm very happy about the improved DRAM clock speed in LIME2. But if I understand this correctly, the old LIME is not expected to be reliable with the DRAM clocked higher than 400MHz? Are you now going to contribute updates for http://git.denx.de/?p=u-boot.git;a=blob;f=configs/A10-OLinuXino-Lime_defconfig;h=8fa1a330cd34e1a8202892595c549971b3275169;hb=HEAD http://git.denx.de/?p=u-boot.git;a=blob;f=configs/A20-OLinuXino-Lime_defconfig;h=5442f645f87165c34bbed8ba3e6cde3d8a8b87e8;hb=HEAD to pick a more reasonable DRAM clock speed? Or do you see no problems having it configured as 480MHz in the mainline u-boot for A10-OLinuXino-Lime and A20-OLinuXino-Lime?" But OLIMEX (Tsvetan Usunov) never bothered replying to this or taking any actions. Despite having been reminded at least once: https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg10402.html I have also added Tsvetan Usunov and Marcus Cooper to CC. Marcus is the maintainer of "A20-Olimex-SOM-EVB" in U-Boot. Hopefully we can make sure that A20-SOM is supported properly. -- Best regards, Siarhei Siamashka -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
