> When the CPU clock speed is set to 480 MHz by the U-Boot SPL,
^^^
You mean MBUS?
> the performance improvement for 'sunxi-fel write' transfers
> to DRAM is ~95 KB/s -> ~510 KB/s.
> When the CPU clock speed is set to 1008 MHz by the U-Boot SPL,
> the performance improvement for 'sunxi-fel write' transfers
> to DRAM is ~180 KB/s -> ~510 KB/s.
I don't understand the relation between the above 2 improvements.
What change causes the speed to go from 95KB/s to 180KB/s?
Stefan
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