On Thu, 28 Jan 2016 14:16:26 +0100
Jens Kuske <[email protected]> wrote:
> after figuring out how to boot a devicetree kernel with allwinner's
> u-boot I only had to add the mandatory
>
> clock-frequency = <24000000>;
> arm,cpu-registers-not-fw-configured;
>
> to the timer node and v4.5-rc1 booted successfully. They are
> intentionally left out in the official dt, because documentation says
> one should prefer to fix the firmware -> mainline u-boot
> No problems with clocks or uart here.
You are right, I had these lines in my DT. Thanks.
But, now, what about the PLL8 (periph1) which should be used by the MMCs?
The A23/A33/H3 (and surely some other SoCs) documentations about
the peripheral/periph/periph0/periph1 PLLs say:
Note: The PLL Output should be fixed to 600MHz, it is not
recommended to vary this value arbitrarily.
(the value is 1.2GHz for the A64)
Could it be safer or simpler to define the frequency of these clocks in
the DT (with their x2/d2)?
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
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