On Mon, 1 Feb 2016 17:39:25 +0000 Andre Przywara <[email protected]> wrote:
> The Allwinner H3 SoC introduced bus clock gates with potentially > different parents per clock gate. The H3 driver chose to hardcode the > actual parent clock relation in the code. > Add a new driver (which has the potential to drive the H3 and also > the simple clock gates as well) which uses the power of DT to describe > this relationship in an elegant and flexible way. > Using one subnode for every parent clock we get away with a single > DT compatible match, which can be used as a fallback value in the > actual DTs without the need to add specific compatible strings to the > code. This avoids adding a new driver or function for every new SoC. > > Signed-off-by: Andre Przywara <[email protected]> > --- > Changelog RFC .. v1: > - fix IRQ muxes to cover the three banks of the SoC > - amend naming of PCM pins > > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk-multi-gates.c | 105 > ++++++++++++++++++++++++++++++++++++ > 2 files changed, 106 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-multi-gates.c [snip] Glad to see that things are moving to the right way. Thanks. Acked-by: Jean-Francois Moine <[email protected]> -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
