With the new generic a31-pll clock driver in place, we can use it to properly describe the PLL8 clock.
Signed-off-by: Andre Przywara <[email protected]> --- arch/arm/boot/dts/sun8i-h3.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 1524130e..1b2eb20 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -137,11 +137,11 @@ clock-output-names = "pll6d2"; }; - /* dummy clock until pll6 can be reused */ - pll8: pll8_clk { + pll8: clk@01c20044 { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; + compatible = "allwinner,sun6i-a31-pll-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; clock-output-names = "pll8"; }; -- 2.6.4 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
