On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote: > On Tue, 8 Mar 2016 08:25:47 +0530 > Vinod Koul <vinod.k...@intel.com> wrote: > > > > Why does dmaengine need to wait? Can you explain that > > I don't have an answer for that one, but when I set WAIT_CYCLES to 1 > for the NAND use case it does not work. So I guess it is somehow > related to how the DRQ line is controlled on the device side...
Is the WAIT cycle different for different usages or same for all usages/channels? -- ~Vinod -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
