Hi,
On Fri, Mar 18, 2016 at 5:44 PM, Andre Przywara <[email protected]> wrote:
> From: Jens Kuske <[email protected]>
>
> Currently, the sunxi clock driver gets the name for the base factor clock
> of divs clocks from the name field in factors_data. This prevents reusing
> of the factor clock for clocks with same properties, but different name.
>
> This commit makes the divs setup function try to get a name from
> clock-output-names in the devicetree. It also removes the name field where
> possible and merges the sun4i PLL5 and PLL6 clocks.
>
> [Andre: Make temporary name allocation dynamic.]
>
> Signed-off-by: Jens Kuske <[email protected]>
> Signed-off-by: Andre Przywara <[email protected]>
> ---
> Hi Maxime,
>
> sorry for the post during the merge window, but I wanted to get this
> going again:
> This is basically Jens' patch, but I removed the fixed 8 character
> name length limitation.
> Briefly tested on BananaPi and Pine64.
>
> Cheers,
> Andre.
This patch looks good overall.
>
> drivers/clk/sunxi/clk-sunxi.c | 40 +++++++++++++++++++++++++++++-----------
> 1 file changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 99f60ef..8dbc5aa 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -523,21 +523,12 @@ static const struct factors_data sun4i_pll5_data
> __initconst = {
> .enable = 31,
> .table = &sun4i_pll5_config,
> .getter = sun4i_get_pll5_factors,
> - .name = "pll5",
> -};
> -
> -static const struct factors_data sun4i_pll6_data __initconst = {
> - .enable = 31,
> - .table = &sun4i_pll5_config,
> - .getter = sun4i_get_pll5_factors,
> - .name = "pll6",
> };
>
> static const struct factors_data sun6i_a31_pll6_data __initconst = {
> .enable = 31,
> .table = &sun6i_a31_pll6_config,
> .getter = sun6i_a31_get_pll6_factors,
> - .name = "pll6x2",
> };
>
> static const struct factors_data sun5i_a13_ahb_data __initconst = {
> @@ -894,7 +885,7 @@ static const struct divs_data pll5_divs_data __initconst
> = {
> };
>
> static const struct divs_data pll6_divs_data __initconst = {
> - .factors = &sun4i_pll6_data,
> + .factors = &sun4i_pll5_data,
> .ndivs = 4,
> .div = {
> { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M,
> SATA */
> @@ -936,6 +927,8 @@ static struct clk ** __init sunxi_divs_clk_setup(struct
> device_node *node,
> struct clk_gate *gate = NULL;
> struct clk_fixed_factor *fix_factor;
> struct clk_divider *divider;
> + struct factors_data factors = *data->factors;
> + char *derived_name = NULL;
> void __iomem *reg;
> int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
> int flags, clkflags;
> @@ -944,9 +937,34 @@ static struct clk ** __init sunxi_divs_clk_setup(struct
> device_node *node,
> if (data->ndivs)
> ndivs = data->ndivs;
>
> + /* Try to find a name for base factor clock */
> + for (i = 0; i < ndivs; i++) {
> + if (data->div[i].self) {
> + of_property_read_string_index(node,
> "clock-output-names",
> + i, &factors.name);
> + break;
> + }
> + }
> + /* If we don't have a .self clk use the first output-name up to '_' */
> + if (factors.name == NULL) {
> + char *endp;
> +
> + of_property_read_string_index(node, "clock-output-names",
> + 0, &clk_name);
> + endp = strchr(clk_name, '_');
> + if (endp) {
> + derived_name = kstrndup(clk_name, endp - clk_name,
> + GFP_KERNEL);
> + factors.name = derived_name;
> + } else {
> + factors.name = clk_name;
I wonder when we'd run into this case.
Regards
ChenYu
> + }
> + }
> +
> /* Set up factor clock that we will be dividing */
> - pclk = sunxi_factors_clk_setup(node, data->factors);
> + pclk = sunxi_factors_clk_setup(node, &factors);
> parent = __clk_get_name(pclk);
> + kfree(derived_name);
>
> reg = of_iomap(node, 0);
>
> --
> 2.7.3
>
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