Hi, On 05/08/16 13:06, Daníel Grétarsson wrote: > Hello, I'm currently working on an embedded Linux board using the Allwinner > H3 > chip and have one question regarding the DRAM data pins connection and > configuration. > > I've been looking at reference schematics from FriendlyARM and NextThingCo's > CHIP computer. > > For example, the CHIP computer connects DQL0 pin of the RAM chip to DQ0 pin > of > the SoC, DQL1 pin on RAM to DQ1 on SoC etc. But looking at FriendlyARM's > NanoPi > M1, the DQL0 pin on RAM is connected to SDQ3 on SoC, DQL1 pin on RAM > connected > to SDQ2 on SoC etc. > > I'm guessing this is done to make the routing on the PCB more convenient. But > I'm having trouble understanding how the SoC knows which pins correspond to > which data lines. Doesn't this need to be configured somewhere? If so, where? > U-boot?
The SoC doesn't care. As long as a bit is read at the same pin where it was written it's irrelevant whether it gets stored at a different bit. Write at SDQ3, stored in bit 0 (DQL0), but read at SDQ3 again, so everything is fine. - bits inside a byte can be swapped - whole bytes can be swapped (including correct DQS/DM lines) - but don't swap bits between bytes Regards, Jens > > i've looked all over the sunxi wiki page, and found a section that talks > about > DRAM configuration, but does not mention the data pins. > > Hope I'm making myself clear enough here. Thanks in advance :) > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
