Hi!

I am trying to get access to the NAND of an unknown Android A33 tablet
device from booting via sdcard. Probably it is an Inet M100_MB v1.1 with
NAND SK Hynix h27ucg8t2bda.

I managed to boot various Android .imgs that are available on the
Internet. When I adb shell to them there is no nand device created in
/dev/ (or /dev/block/, which seems to be the place for the original
nandX of the device).

The driver nand.ko gets loaded in all images, I have found output in
dmesg of one of them which is at the end of this mail.

>From my perspective there are some errors but it seems that the
initialization kind of worked. I have no comparable output though.

I do not have adb access to the original ROM of the device in question.
I cannot get the stock ROM for the device, neither the code.

My questions are:
1) Does the output look normal?
2) Which bootloaders can access the NAND of the device, maybe I should
not boot a complete image but rather only the bootloader to access the NAND?
3) Must I touch nand.ko source to add the IDs of this specific NAND to
make it work?
4) Is /dev/nandX normally created if you boot from sdcard? Maybe I am
missing some boot/config flags?

Cheers and thanks,

Florian

<4>[    2.602705] [NAND][NAND]nand init start, nand0_used_flag is 1
<4>[    2.602724] [NAND]nand_cache_level err! 0[NAND]nand_capacity_level
err! 0
<4>[    2.602737] regisger ISP =====================
<4>[    2.602776] [NAND]nand init start
<4>[    2.602784] NandHwInit: Start Nand Hardware initializing .....
<4>[    2.602793] kernel:physical version: 2 19 20140605 1640
<4>[    2.602813] [NAND] channel cnt is 1
<4>[    2.602821] ndfc version: 1
<4>[    2.602828] ndfc dma mode: MBUS DMA
<4>[    2.602836] pin count:19
<4>[    2.602963] NAND_ClkRequest: get pll6 rate 600000000HZ
<4>[    2.603125] axp22_dcdc1: Failed to create debugfs directory
<4>[    2.603241] nand:get voltage axp22_dcdc1 ok:def58840
<4>[    2.603252] Reset NDFC 0
<4>[    2.603261] NFC Randomizer start.
<4>[    2.603272] NFC_ResetChip: 0x101, 0x100 0x10095
<4>[    2.603280] NFC_ResetChip: 0xff, ch: 0
<4>[    2.604473] [PHY_DBG] CH 0 Nand flash chip id is:0xad 0xde 0x94
0xeb 0x74 0x44
<4>[    2.604483] nand id of two channel is not the same, set to 1
channel mode
<4>[    2.604494] [SCAN_DBG] Nand flash chip id is:0xad 0xde 0x94 0xeb
0x74 0x44
<4>[    2.604511] [SCAN_DBG] NandTwoPlaneOp: 1, DriverTwoPlaneOPCfg: 1,
0xffeffddf
<4>[    2.604524] nand_para0, id_number_ctl, nand type err! 0
<4>[    2.604532] _UpdateExtAccessFreqPara: no para.
<4>[    2.604542] NFC_ResetChip: 0x1000101, 0x100 0x10095
<4>[    2.604550] NFC_ResetChip: 0xff, ch: 0
<4>[    2.604577] [PHY_DBG] CH 0 Nand flash chip id is:0x0 0x0 0x0 0x0
0x0 0x0
<4>[    2.604587] NFC_ResetChip: 0x2000109, 0x100 0x10095
<4>[    2.604596] NFC_ResetChip: 0xff, ch: 0
<4>[    2.604623] [PHY_DBG] CH 0 Nand flash chip id is:0x0 0x0 0x0 0x0
0x0 0x0
<4>[    2.604633] NFC_ResetChip: 0x3000109, 0x100 0x10095
<4>[    2.604641] NFC_ResetChip: 0xff, ch: 0
<4>[    2.604668] [PHY_DBG] CH 0 Nand flash chip id is:0x0 0x0 0x0 0x0
0x0 0x0
<4>[    2.604678] Reset NDFC 0
<4>[    2.604688] PageCachePool.PageCache0: 0xdfb10000
<4>[    2.604802] PageCachePool.PageCache1: 0xde950000
<4>[    2.604911] PageCachePool.PageCache2: 0xdeb10000
<4>[    2.605020] PageCachePool.PageCache3: 0xde960000
<4>[    2.605124] PageCachePool.PageCache4: 0xde970000
<4>[    2.605134] PageCachePool.SpareCache: 0xde817a00
<4>[    2.605236] PageCachePool.TmpPageCache: 0xdeb20000
<4>[    2.605334] PageCachePool.TmpPageCache1: 0xdeb30000
<4>[    2.605348] PHY_ChangeMode: sclk0 will be changed! 10 -> 40
<4>[    2.605360] PHY_ChangeMode: before check blank page, 0x401, 0x100,
0x10095, 0x21f
<4>[    2.606601] _check_scan_data, ok, block 2
<4>[    2.606612] _check_scan_data, valid data for ddr scan, block 2
<4>[    2.606621] PHY_ChangeMode: valid burned data!
<4>[    2.606631] PHY_ChangeMode: timing_change 1,  sclk0_bak 10, sclk0 40!
<4>[    2.606655] _get_right_timing_para, set edo to 1 for sdr nand.
<4>[    2.606666] NFC Read Retry Init.
<4>[    2.607321] ch: 0, chip 0, block 8, page 0, oob: 0x0, 0x4f, 0x4f, 0x43
<4>[    2.607333] find good otp value in ch: 0, chip 0, block 8
<4>[    2.607343] ch 0, Read Retry value Table from nand otp block:
<4>[    2.607351] 0x33 0x49 0x62 0xad 0x45 0x49 0x62 0xad
<4>[    2.607377] 0x3d 0x4d 0x66 0xaf 0x4f 0x4d 0x66 0xaf
<4>[    2.607403] 0x3b 0x50 0x60 0xa8 0x4d 0x50 0x60 0xa8
<4>[    2.607429] 0x39 0x43 0x5e 0xa3 0x4b 0x43 0x5e 0xa3
<4>[    2.607455] 0x35 0x41 0x5c 0xa1 0x47 0x41 0x5c 0xa1
<4>[    2.607480] 0x2e 0x3f 0x5a 0x9d 0x40 0x3f 0x5a 0x9d
<4>[    2.607506] 0x24 0x3c 0x58 0x99 0x36 0x3c 0x58 0x99
<4>[    2.607532] 0x1a 0x26 0x42 0x87 0x2c 0x26 0x42 0x87
<4>[    2.607592] set retry default value:  33 49 62 ad 45 49 62 ad
<4>[    2.608295] _GetOldPhysicArch: ch: 0, chip 0, block 12, page 0,
oob: 0x0, 0x50, 0x48, 0x59
<4>[    2.608309] _GetOldPhysicArch: get old physic arch ok, 0x3180 0x1!
<4>[    2.608320] NAND_ReadPhyArch: get old physic arch ok, use old cfg,
now:0x2 0x3188 - old:0x1 0x3180!
<4>[    2.608330]
<4>[    2.608333]
<4>[    2.608339] [SCAN_DBG] ==============Nand Architecture
Parameter==============
<4>[    2.608349] [SCAN_DBG]    Nand Chip ID:         0xeb94dead 0xffffff74
<4>[    2.608358] [SCAN_DBG]    Nand Channel Count:   0x1
<4>[    2.608366] [SCAN_DBG]    Nand Chip Count:      0x1
<4>[    2.608373] [SCAN_DBG]    Nand Chip Connect:    0x1
<4>[    2.608381] [SCAN_DBG]    Nand Rb Connect Mode:      0x1
<4>[    2.608389] [SCAN_DBG]    Sector Count Of Page: 0x20
<4>[    2.608397] [SCAN_DBG]    Page Count Of Block:  0x100
<4>[    2.608405] [SCAN_DBG]    Block Count Of Die:   0x800
<4>[    2.608413] [SCAN_DBG]    Plane Count Of Die:   0x1
<4>[    2.608420] [SCAN_DBG]    Die Count Of Chip:    0x1
<4>[    2.608428] [SCAN_DBG]    Bank Count Of Chip:   0x1
<4>[    2.608436] [SCAN_DBG]    Optional Operation:   0x3180
<4>[    2.608444] [SCAN_DBG]    Access Frequency:     0x28
<4>[    2.608452] [SCAN_DBG]    ECC Mode:             0x4
<4>[    2.608460] [SCAN_DBG]    Read Retry Type:      0x30708
<4>[    2.608467] [SCAN_DBG]    DDR Type:             0x0
<4>[    2.608475] [SCAN_DBG]
=======================================================
<4>[    2.608480]
<4>[    2.608487] [SCAN_DBG] ==============Optional Operaion
Parameter==============
<4>[    2.608497] [SCAN_DBG]    MultiPlaneReadCmd:      0x60, 0x60
<4>[    2.608505] [SCAN_DBG]    MultiPlaneWriteCmd:     0x11, 0x81
<4>[    2.608514] [SCAN_DBG]    MultiPlaneCopyReadCmd:  0x60, 0x60, 0x35
<4>[    2.608524] [SCAN_DBG]    MultiPlaneCopyWriteCmd: 0x85, 0x11, 0x81
<4>[    2.608533] [SCAN_DBG]    MultiPlaneStatusCmd:    0x70
<4>[    2.608541] [SCAN_DBG]    InterBnk0StatusCmd:     0xf1
<4>[    2.608549] [SCAN_DBG]    InterBnk1StatusCmd:     0xf2
<4>[    2.608556] [SCAN_DBG]    BadBlockFlagPosition:   0x2
<4>[    2.608564] [SCAN_DBG]    MultiPlaneBlockOffset:  0x1
<4>[    2.608572] [SCAN_DBG]
=======================================================
<4>[    2.608583] kernel:nand info: eb94dead ffffff74 3180 30708 4
<4>[    2.608606]
<4>[    2.608612] [FORMAT_DBG] ===========Logical Architecture
Parameter===========
<4>[    2.608621] [FORMAT_DBG]    Page Count of Logic Block:  0x100
<4>[    2.608630] [FORMAT_DBG]    Sector Count of Logic Page: 0x20
<4>[    2.608638] [FORMAT_DBG]    Block Count of Die:         0x800
<4>[    2.608647] [FORMAT_DBG]    Die Count:                  0x1
<4>[    2.608655] [FORMAT_DBG]
===================================================
<4>[    2.608666] NandHwInit: End Nand Hardware initializing ..... OK!
<4>[    2.608680] [NAND]storage_type=1,run nand test for dragonboard

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