On Fri, Feb 10, 2017 at 11:42:34AM +0800, Chen-Yu Tsai wrote:
> The GR8, like other sun5i SoCs, has only 1 pin option for PWM0 output.
> Other SoCs had named the pingroup "pwm0_pins" in their dtsi files, while
> GR8 named it "pwm0_pins_a". When we switched to the new common sun5i
> dtsi file, we forgot to rename the pingroup references in the GR8 board
> dts files.
>
> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
> ---
>
> Fixes: a2138ce584d5 ("ARM: sun5i: gr8: Use common sun5i DTSI")Squashed it in the previous patch. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
signature.asc
Description: PGP signature
