On 13/03/17 17:50, Icenowy Zheng wrote:
> The DesignWare-like DRAM code used to set the controller defaultly to
> single rank mode, which makes it not able to detect the second rank.
>
> Set the default value to dual rank, thus the rank detection code can
> work and finally the rank setting will be the correct value.
>
> This change is tested on a Orange Pi One (H3, single rank), a Pine64+
> 2GiB version (A64, single rank) , a Pinebook early prototype with DDR3
> (A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins
> on one chip).
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Reviewed-by: Andre Przywara <andre.przyw...@arm.com>
Cheers,
Andre.
> ---
> arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c
> b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> index 3629d34f71..e1ea6845df 100644
> --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
> +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> @@ -543,7 +543,7 @@ unsigned long sunxi_dram_init(void)
> (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
>
> struct dram_para para = {
> - .dual_rank = 0,
> + .dual_rank = 1,
> .bus_full_width = 1,
> .row_bits = 15,
> .bank_bits = 3,
>
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