On Fri, Mar 24, 2017 at 04:33:07PM +0800, Chen-Yu Tsai wrote:
> We ignore the d1 and d2 dividers in the audio PLL, and force them to
> 1 (register value 0) at probe time. However the comment preceding the
> audio PLL definition says we enforce the default value, which is not
> the same.
>
> Fix the preceding comment to match what we do in code.
>
> Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
> Signed-off-by: Chen-Yu Tsai <w...@csie.org>Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
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