On Fri, Jul 14, 2017 at 02:42:55PM +0800, Chen-Yu Tsai wrote: > The register for the "new timing mode" also has bit fields for setting > output and sample timing phases. According to comments in Allwinner's > BSP kernel, the default values are good enough. > > Keep the default values already in the hardware when setting new timing > mode, instead of overwriting the whole register. > > Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC > controllers") > Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
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