Hi, there's some pattern. This is the lookup table that the BSP driver uses:
https://github.com/megous/h3-firmware/blob/master/clk.c#L166 If you stray too much from this you'll get PLL lockups on change and have to do some acrobatics to restart the PLL, which is kind of pointless if it can be avoided. And it can be avoided. Basically the rules are: M = 0 P > 0 only for freqs < 240MHz K as low as possible for the target frequency N arbitrary If you stick to this, you'll not get any problems and will not need any workarounds. regards, o. Mark L. píše v Ne 22. 10. 2017 v 10:33 +0200: > Hi, > > The formula for the PLL CPUX output is (24Mhz * N * K) / (M * P). > Is there a problem applying N = 32 && K = 2 instead of N = 16 and K = 4 (M > and P being equal)? > > I am asking if there is a pattern to respect or not at all. > > Thanks > > -- > Mark > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
signature.asc
Description: This is a digitally signed message part
