clock gating bits on a64 are different than H3_H5, so fixed
only required bits on clock_sun6i.h.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d35aa479f7..c5dea45985 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -271,21 +271,27 @@ struct sunxi_ccm_reg {
#define AXI_GATE_OFFSET_DRAM 0
/* ahb_gate0 offsets */
-#define AHB_GATE_OFFSET_USB_OHCI1 30
-#define AHB_GATE_OFFSET_USB_OHCI0 29
#ifdef CONFIG_MACH_SUNXI_H3_H5
/*
* These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
* them 0 - 2 like they were called on older SoCs.
*/
+#define AHB_GATE_OFFSET_USB_OHCI0 28
#define AHB_GATE_OFFSET_USB_EHCI2 27
#define AHB_GATE_OFFSET_USB_EHCI1 26
+#define AHB_GATE_OFFSET_USB_EHCI0 24
+#elif defined(CONFIG_MACH_SUN50I)
+#define AHB_GATE_OFFSET_USB_OHCI0 29
#define AHB_GATE_OFFSET_USB_EHCI0 25
#else
+#define AHB_GATE_OFFSET_USB_OHCI1 30
+#define AHB_GATE_OFFSET_USB_OHCI0 29
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
#endif
-#ifndef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN50I
+#define AHB_GATE_OFFSET_USB0 23
+#elif !defined(CONFIG_MACH_SUN8I_R40)
#define AHB_GATE_OFFSET_USB0 24
#else
#define AHB_GATE_OFFSET_USB0 25
--
2.14.3
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