On 04/04/2018 06:31 PM, Jagan Teki wrote:
On 04/04/2018 05:24 PM, Chen-Yu Tsai wrote:
On Wed, Apr 4, 2018 at 7:09 PM, Jagan Teki <ja...@openedev.com> wrote:
On 04/04/2018 04:31 PM, Jagan Teki wrote:
On 04/03/2018 04:09 PM, Chen-Yu Tsai wrote:
On Tue, Apr 3, 2018 at 6:31 PM, Jagan Teki <ja...@openedev.com> wrote:
On 04/03/2018 03:16 PM, Chen-Yu Tsai wrote:
On Tue, Apr 3, 2018 at 5:43 PM, Jagan Teki <ja...@openedev.com>
wrote:
On 04/03/2018 03:02 PM, Chen-Yu Tsai wrote:
On Tue, Apr 3, 2018 at 5:27 PM, Jagan Teki <ja...@openedev.com>
wrote:
On 04/03/2018 02:26 PM, Chen-Yu Tsai wrote:
On Tue, Apr 3, 2018 at 3:29 PM, Jagan Teki <ja...@openedev.com>
wrote:
On 04/03/2018 12:19 PM, Chen-Yu Tsai wrote:
On Tue, Apr 3, 2018 at 2:44 PM, Jagan Teki
<ja...@openedev.com>
wrote:
Hi,
Anyone observed SDIO CMD5 timeout for A64 boards.?
I've custom board runs with linux-next and I'm unable to
probe
SDIO
on
mmc1, observed CMD5 timeout.
Here is the log and dts node, request for any help?
Log:
[ 0.340446] sunxi-mmc 1c10000.mmc: could not find
pctldev for
node
/soc/pinctrl@1c20800/mmc1-pins, deferring p
robe
[ 1.927883] mmc1: clock 0Hz busmode 2 powermode 1 cs 0
Vdd 21
width
1 timing 0
[ 1.948765] mmc1: clock 400000Hz busmode 2 powermode 2
cs 0
Vdd
21
width 1 timing 0
[ 2.008318] mmc1: mmc_rescan_try_freq: trying to init
card at
400000
Hz
[ 2.018121] mmc1: starting CMD52 arg 00000c00 flags
00000195
[ 2.055592] mmc1: req done (CMD52): -110: 00000000
00000000
00000000
00000000
[ 2.064813] mmc1: starting CMD52 arg 80000c08 flags
00000195
[ 2.078524] mmc1: req done (CMD52): -110: 00000000
00000000
00000000
00000000
[ 2.095536] mmc1: clock 400000Hz busmode 2 powermode 2
cs 1
Vdd
21
width 1 timing 0
[ 2.108250] mmc1: starting CMD0 arg 00000000 flags
000000c0
[ 2.115158] mmc1: req done (CMD0): 0: 00000000 00000000
00000000
00000000
[ 2.132065] mmc1: clock 400000Hz busmode 2 powermode 2
cs 0
Vdd
21
width 1 timing 0
[ 2.143698] mmc1: starting CMD8 arg 000001aa flags
000002f5
[ 2.155126] mmc1: req done (CMD8): -110: 00000000 00000000
00000000
00000000
[ 2.164988] mmc1: starting CMD5 arg 00000000 flags
000002e1
[ 2.175369] mmc1: req failed (CMD5): -110, retrying...
[ 2.185932] mmc1: req failed (CMD5): -110, retrying...
[ 2.196754] mmc1: req failed (CMD5): -110, retrying...
dt node:
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2
GPIO_ACTIVE_LOW>;
/*
WL-PMU-EN:
PL2 */
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <®_aldo1>;
vqmmc-supply = <®_dldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&r_pio>;
interrupts = <0 3
IRQ_TYPE_LEVEL_LOW>; /*
WL-WAKE-AP:
PL3 */
interrupt-names = "host-wake";
};
};
Are you certain everything is powered up? On some boards
they use
different
regulators for vqmmc on the WiFi chip and pin VCC on the SoC
side.
Also
try
Yes, I didn't find much different in regulator setup on vqmmc,
vmmc
it
is
similar to bananapi-m64 which is drive to dldo4 for vqmmc and
aldo1
for
vmmc
like this
vqmmc:
DLDO4 VCC-PG VCC-IO-WIFI
| | |
|------------|--------|
|
ELDO1 |
|------------|
Have you tried enabling both regulators?
At same time no? I've tried one after another.
Well, it's possible that one feeds VCC-PG and the other
VCC-IO-WIFI.
So you need to enable both.
I never see how to enable both same for vqmmc, is it something like
this?
vqmmc-supply = <®_dldo4 ®_eldo1>;
You can't. Not yet anyway. Just set one of them to "always on",
preferably
the one for the SoC side, as using any other pins in that pin group
would
look like VCC-PG is from processor side, set the same eldo1 to
regulator-always-on and vqmmc-supply = <reg_dldo4>
also require it to be powered.
What do you mean by pin group here? does that mean linking other
supplies
which are attached to same regulator like eldo1 here?
As the name VCC-PG implies, it provides power to the PG pingroup.
So if
the board uses any of the other PG pins for things such as GPIOs or
other
peripherals, you will need to power it regardless of whether WiFi
is on
or not. I suggest you read up on the datasheets which explain what pin
does what.
Yes we have PG group GPIO's which is similar to bananapi-m64 like
PG0-PG13
I have power it the all. Wouldn't find any change in behavior. I've
XTAL-IN
and XTAL-OUT on pin10 and 11 with 26MHz like orangepi-win would that
clock
effect? attached oragepi-win schematics please see on page 13.
What I mean to say here is, osc24M and osc32k added in sun50-a64.dtsi no
clock for osc26M is it really need?
No. Because there is no binding for it, and the WiFi chip is supposed to
automatically detect it anyway. Are you using a Broadcom-based solution?
That includes the AP6??? modules. If so, you need to a 32768 Hz clock
signal to it prior to powering it on, so that the chip can detect the
frequency of the XTAL. This is mentioned in Broadcom's datasheets. Some
can work without, others can't. YMMV.
yes true, we have AP6330 chip.
Your device tree is missing that. Typically we specify that clock
in the pwrseq node. See the bindings for that. The source would depend
on your board design.
Yes, I've tried few already with using exiting binding from
sun50i-a64.dtsi and specifying explicitly like these
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
clocks = <&osc32k>;
clock-names = "xin32k";
};
And
wifi_osc32k: wifi-osc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
clocks = <&wifi_osc32k>;
clock-names = "xin32k";
};
Any further help on this?
I didn't see any external clock connection in A64 board like AC100 RTC
in cubietruc like you added [2]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts?id=f346019be711dc0bc10d40e8510644005e38d53a
Pls. let me know if you have any inputs.
Jagan.
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