Updates the device tree file from the the Linux tree as of v4.17-rc5,
exactly Linux commit:
commit c1cff65f9b16b31e731e2e75bbe06638c86e1996
Author: Harald Geyer <har...@ccbib.org>
Date:   Thu Mar 15 16:25:08 2018 +0000

    arm64: dts: allwinner: a64: add simplefb for A64 SoC

This also pulls in the newly required include files for the clock and
reset bindings, also removes the now redundant part from our
*-u-boot.dtsi overlay file.

Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
---
 arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi |  61 +----
 arch/arm/dts/sun50i-a64.dtsi                    | 303 +++++++++++++++++++++---
 include/dt-bindings/clock/sun8i-r-ccu.h         |  59 +++++
 include/dt-bindings/reset/sun8i-r-ccu.h         |  53 +++++
 4 files changed, 398 insertions(+), 78 deletions(-)
 create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi 
b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
index 32a263ce3d..1b8aa3d8dc 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
@@ -2,58 +2,19 @@
        aliases {
                ethernet0 = &emac;
        };
-
-       soc {
-               syscon: syscon@1c00000 {
-                       compatible = "allwinner,sun50i-a64-system-controller",
-                                    "syscon";
-                       reg = <0x01c00000 0x1000>;
-               };
-
-               emac: ethernet@1c30000 {
-                       compatible = "allwinner,sun50i-a64-emac";
-                       syscon = <&syscon>;
-                       reg = <0x01c30000 0x10000>;
-                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "macirq";
-                       resets = <&ccu RST_BUS_EMAC>;
-                       reset-names = "stmmaceth";
-                       clocks = <&ccu CLK_BUS_EMAC>;
-                       clock-names = "stmmaceth";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&rgmii_pins>;
-                       phy-mode = "rgmii";
-                       phy-handle = <&ext_rgmii_phy>;
-                       status = "okay";
-
-                       mdio: mdio {
-                               compatible = "snps,dwmac-mdio";
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               ext_rgmii_phy: ethernet-phy@1 {
-                                       compatible = 
"ethernet-phy-ieee802.3-c22";
-                                       reg = <1>;
-                               };
-                       };
-               };
-       };
 };
 
-&pio {
-       rmii_pins: rmii_pins {
-               pins = "PD10", "PD11", "PD13", "PD14", "PD17",
-                      "PD18", "PD19", "PD20", "PD22", "PD23";
-               function = "emac";
-               drive-strength = <40>;
-       };
+&emac {
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmii_pins>;
+       phy-mode = "rgmii";
+       phy-handle = <&ext_rgmii_phy>;
+       status = "okay";
+};
 
-       rgmii_pins: rgmii_pins {
-               pins = "PD8", "PD9", "PD10", "PD11", "PD12",
-                      "PD13", "PD15", "PD16", "PD17", "PD18",
-                      "PD19", "PD20", "PD21", "PD22", "PD23";
-               function = "emac";
-               drive-strength = <40>;
+&mdio {
+       ext_rgmii_phy: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <1>;
        };
 };
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 65a344d9ce..1b2ef28c42 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -43,6 +43,7 @@
  */
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
@@ -51,6 +52,26 @@
        #address-cells = <1>;
        #size-cells = <1>;
 
+       chosen {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+/*
+ * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
+ * However there is no support for this clock on A64 yet, so we depend
+ * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
+ */
+               simplefb_lcd: framebuffer-lcd {
+                       compatible = "allwinner,simple-framebuffer",
+                                    "simple-framebuffer";
+                       allwinner,pipeline = "mixer0-lcd0";
+                       clocks = <&ccu CLK_TCON0>,
+                                <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+                       status = "disabled";
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -111,6 +132,24 @@
                method = "smc";
        };
 
+       sound_spdif {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "On-board SPDIF";
+
+               simple-audio-card,cpu {
+                       sound-dai = <&spdif>;
+               };
+
+               simple-audio-card,codec {
+                       sound-dai = <&spdif_out>;
+               };
+       };
+
+       spdif_out: spdif-out {
+               #sound-dai-cells = <0>;
+               compatible = "linux,spdif-dit";
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 13
@@ -129,6 +168,23 @@
                #size-cells = <1>;
                ranges;
 
+               syscon: syscon@1c00000 {
+                       compatible = "allwinner,sun50i-a64-system-controller",
+                               "syscon";
+                       reg = <0x01c00000 0x1000>;
+               };
+
+               dma: dma-controller@1c02000 {
+                       compatible = "allwinner,sun50i-a64-dma";
+                       reg = <0x01c02000 0x1000>;
+                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_DMA>;
+                       dma-channels = <8>;
+                       dma-requests = <27>;
+                       resets = <&ccu RST_BUS_DMA>;
+                       #dma-cells = <1>;
+               };
+
                mmc0: mmc@1c0f000 {
                        compatible = "allwinner,sun50i-a64-mmc";
                        reg = <0x01c0f000 0x1000>;
@@ -171,7 +227,7 @@
                        #size-cells = <0>;
                };
 
-               usb_otg: usb@01c19000 {
+               usb_otg: usb@1c19000 {
                        compatible = "allwinner,sun8i-a33-musb";
                        reg = <0x01c19000 0x0400>;
                        clocks = <&ccu CLK_BUS_OTG>;
@@ -184,7 +240,7 @@
                        status = "disabled";
                };
 
-               usbphy: phy@01c19400 {
+               usbphy: phy@1c19400 {
                        compatible = "allwinner,sun50i-a64-usb-phy";
                        reg = <0x01c19400 0x14>,
                              <0x01c1a800 0x4>,
@@ -204,7 +260,7 @@
                        #phy-cells = <1>;
                };
 
-               ehci0: usb@01c1a000 {
+               ehci0: usb@1c1a000 {
                        compatible = "allwinner,sun50i-a64-ehci", 
"generic-ehci";
                        reg = <0x01c1a000 0x100>;
                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -216,7 +272,7 @@
                        status = "disabled";
                };
 
-               ohci0: usb@01c1a400 {
+               ohci0: usb@1c1a400 {
                        compatible = "allwinner,sun50i-a64-ohci", 
"generic-ohci";
                        reg = <0x01c1a400 0x100>;
                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
@@ -226,7 +282,7 @@
                        status = "disabled";
                };
 
-               ehci1: usb@01c1b000 {
+               ehci1: usb@1c1b000 {
                        compatible = "allwinner,sun50i-a64-ehci", 
"generic-ehci";
                        reg = <0x01c1b000 0x100>;
                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
@@ -240,7 +296,7 @@
                        status = "disabled";
                };
 
-               ohci1: usb@01c1b400 {
+               ohci1: usb@1c1b400 {
                        compatible = "allwinner,sun50i-a64-ohci", 
"generic-ohci";
                        reg = <0x01c1b400 0x100>;
                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -252,7 +308,7 @@
                        status = "disabled";
                };
 
-               ccu: clock@01c20000 {
+               ccu: clock@1c20000 {
                        compatible = "allwinner,sun50i-a64-ccu";
                        reg = <0x01c20000 0x400>;
                        clocks = <&osc24M>, <&osc32k>;
@@ -273,6 +329,11 @@
                        interrupt-controller;
                        #interrupt-cells = <3>;
 
+                       i2c0_pins: i2c0_pins {
+                               pins = "PH0", "PH1";
+                               function = "i2c0";
+                       };
+
                        i2c1_pins: i2c1_pins {
                                pins = "PH2", "PH3";
                                function = "i2c1";
@@ -303,7 +364,37 @@
                                bias-pull-up;
                        };
 
-                       uart0_pins_a: uart0@0 {
+                       rmii_pins: rmii_pins {
+                               pins = "PD10", "PD11", "PD13", "PD14", "PD17",
+                                      "PD18", "PD19", "PD20", "PD22", "PD23";
+                               function = "emac";
+                               drive-strength = <40>;
+                       };
+
+                       rgmii_pins: rgmii_pins {
+                               pins = "PD8", "PD9", "PD10", "PD11", "PD12",
+                                      "PD13", "PD15", "PD16", "PD17", "PD18",
+                                      "PD19", "PD20", "PD21", "PD22", "PD23";
+                               function = "emac";
+                               drive-strength = <40>;
+                       };
+
+                       spdif_tx_pin: spdif {
+                               pins = "PH8";
+                               function = "spdif";
+                       };
+
+                       spi0_pins: spi0 {
+                               pins = "PC0", "PC1", "PC2", "PC3";
+                               function = "spi0";
+                       };
+
+                       spi1_pins: spi1 {
+                               pins = "PD0", "PD1", "PD2", "PD3";
+                               function = "spi1";
+                       };
+
+                       uart0_pins_a: uart0 {
                                pins = "PB8", "PB9";
                                function = "uart0";
                        };
@@ -317,6 +408,70 @@
                                pins = "PG8", "PG9";
                                function = "uart1";
                        };
+
+                       uart2_pins: uart2-pins {
+                               pins = "PB0", "PB1";
+                               function = "uart2";
+                       };
+
+                       uart3_pins: uart3-pins {
+                               pins = "PD0", "PD1";
+                               function = "uart3";
+                       };
+
+                       uart4_pins: uart4-pins {
+                               pins = "PD2", "PD3";
+                               function = "uart4";
+                       };
+
+                       uart4_rts_cts_pins: uart4-rts-cts-pins {
+                               pins = "PD4", "PD5";
+                               function = "uart4";
+                       };
+               };
+
+               spdif: spdif@1c21000 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun50i-a64-spdif",
+                                    "allwinner,sun8i-h3-spdif";
+                       reg = <0x01c21000 0x400>;
+                       interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+                       resets = <&ccu RST_BUS_SPDIF>;
+                       clock-names = "apb", "spdif";
+                       dmas = <&dma 2>;
+                       dma-names = "tx";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spdif_tx_pin>;
+                       status = "disabled";
+               };
+
+               i2s0: i2s@1c22000 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun50i-a64-i2s",
+                                    "allwinner,sun8i-h3-i2s";
+                       reg = <0x01c22000 0x400>;
+                       interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+                       clock-names = "apb", "mod";
+                       resets = <&ccu RST_BUS_I2S0>;
+                       dma-names = "rx", "tx";
+                       dmas = <&dma 3>, <&dma 3>;
+                       status = "disabled";
+               };
+
+               i2s1: i2s@1c22400 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun50i-a64-i2s",
+                                    "allwinner,sun8i-h3-i2s";
+                       reg = <0x01c22400 0x400>;
+                       interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+                       clock-names = "apb", "mod";
+                       resets = <&ccu RST_BUS_I2S1>;
+                       dma-names = "rx", "tx";
+                       dmas = <&dma 4>, <&dma 4>;
+                       status = "disabled";
                };
 
                uart0: serial@1c28000 {
@@ -325,8 +480,8 @@
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&ccu 67>;
-                       resets = <&ccu 46>;
+                       clocks = <&ccu CLK_BUS_UART0>;
+                       resets = <&ccu RST_BUS_UART0>;
                        status = "disabled";
                };
 
@@ -336,8 +491,8 @@
                        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&ccu 68>;
-                       resets = <&ccu 47>;
+                       clocks = <&ccu CLK_BUS_UART1>;
+                       resets = <&ccu RST_BUS_UART1>;
                        status = "disabled";
                };
 
@@ -347,8 +502,8 @@
                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&ccu 69>;
-                       resets = <&ccu 48>;
+                       clocks = <&ccu CLK_BUS_UART2>;
+                       resets = <&ccu RST_BUS_UART2>;
                        status = "disabled";
                };
 
@@ -358,8 +513,8 @@
                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&ccu 70>;
-                       resets = <&ccu 49>;
+                       clocks = <&ccu CLK_BUS_UART3>;
+                       resets = <&ccu RST_BUS_UART3>;
                        status = "disabled";
                };
 
@@ -369,8 +524,8 @@
                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&ccu 71>;
-                       resets = <&ccu 50>;
+                       clocks = <&ccu CLK_BUS_UART4>;
+                       resets = <&ccu RST_BUS_UART4>;
                        status = "disabled";
                };
 
@@ -378,8 +533,8 @@
                        compatible = "allwinner,sun6i-a31-i2c";
                        reg = <0x01c2ac00 0x400>;
                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu 63>;
-                       resets = <&ccu 42>;
+                       clocks = <&ccu CLK_BUS_I2C0>;
+                       resets = <&ccu RST_BUS_I2C0>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -389,8 +544,8 @@
                        compatible = "allwinner,sun6i-a31-i2c";
                        reg = <0x01c2b000 0x400>;
                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu 64>;
-                       resets = <&ccu 43>;
+                       clocks = <&ccu CLK_BUS_I2C1>;
+                       resets = <&ccu RST_BUS_I2C1>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -400,11 +555,67 @@
                        compatible = "allwinner,sun6i-a31-i2c";
                        reg = <0x01c2b400 0x400>;
                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu 65>;
-                       resets = <&ccu 44>;
+                       clocks = <&ccu CLK_BUS_I2C2>;
+                       resets = <&ccu RST_BUS_I2C2>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+
+               spi0: spi@1c68000 {
+                       compatible = "allwinner,sun8i-h3-spi";
+                       reg = <0x01c68000 0x1000>;
+                       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+                       clock-names = "ahb", "mod";
+                       dmas = <&dma 23>, <&dma 23>;
+                       dma-names = "rx", "tx";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spi0_pins>;
+                       resets = <&ccu RST_BUS_SPI0>;
+                       status = "disabled";
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               spi1: spi@1c69000 {
+                       compatible = "allwinner,sun8i-h3-spi";
+                       reg = <0x01c69000 0x1000>;
+                       interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+                       clock-names = "ahb", "mod";
+                       dmas = <&dma 24>, <&dma 24>;
+                       dma-names = "rx", "tx";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spi1_pins>;
+                       resets = <&ccu RST_BUS_SPI1>;
+                       status = "disabled";
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               emac: ethernet@1c30000 {
+                       compatible = "allwinner,sun50i-a64-emac";
+                       syscon = <&syscon>;
+                       reg = <0x01c30000 0x10000>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq";
+                       resets = <&ccu RST_BUS_EMAC>;
+                       reset-names = "stmmaceth";
+                       clocks = <&ccu CLK_BUS_EMAC>;
+                       clock-names = "stmmaceth";
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
+
+                       mdio: mdio {
+                               compatible = "snps,dwmac-mdio";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
                };
 
                gic: interrupt-controller@1c81000 {
@@ -425,25 +636,61 @@
                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               r_intc: interrupt-controller@1f00c00 {
+                       compatible = "allwinner,sun50i-a64-r-intc",
+                                    "allwinner,sun6i-a31-r-intc";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       reg = <0x01f00c00 0x400>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
                r_ccu: clock@1f01400 {
                        compatible = "allwinner,sun50i-a64-r-ccu";
                        reg = <0x01f01400 0x100>;
-                       clocks = <&osc24M>, <&osc32k>, <&iosc>;
-                       clock-names = "hosc", "losc", "iosc";
+                       clocks = <&osc24M>, <&osc32k>, <&iosc>,
+                                <&ccu 11>;
+                       clock-names = "hosc", "losc", "iosc", "pll-periph";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                };
 
-               r_pio: pinctrl@01f02c00 {
+               r_pio: pinctrl@1f02c00 {
                        compatible = "allwinner,sun50i-a64-r-pinctrl";
                        reg = <0x01f02c00 0x400>;
                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+                       clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
                        clock-names = "apb", "hosc", "losc";
                        gpio-controller;
                        #gpio-cells = <3>;
                        interrupt-controller;
                        #interrupt-cells = <3>;
+
+                       r_rsb_pins: rsb {
+                               pins = "PL0", "PL1";
+                               function = "s_rsb";
+                       };
+               };
+
+               r_rsb: rsb@1f03400 {
+                       compatible = "allwinner,sun8i-a23-rsb";
+                       reg = <0x01f03400 0x400>;
+                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&r_ccu 6>;
+                       clock-frequency = <3000000>;
+                       resets = <&r_ccu 2>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&r_rsb_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               wdt0: watchdog@1c20ca0 {
+                       compatible = "allwinner,sun50i-a64-wdt",
+                                    "allwinner,sun6i-a31-wdt";
+                       reg = <0x01c20ca0 0x20>;
+                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                };
        };
 };
diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h 
b/include/dt-bindings/clock/sun8i-r-ccu.h
new file mode 100644
index 0000000000..779d20aa0d
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r-ccu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icen...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+
+#define CLK_AR100              0
+
+#define CLK_APB0_PIO           3
+#define CLK_APB0_IR            4
+#define CLK_APB0_TIMER         5
+#define CLK_APB0_RSB           6
+#define CLK_APB0_UART          7
+/* 8 is reserved for CLK_APB0_W1 on A31 */
+#define CLK_APB0_I2C           9
+#define CLK_APB0_TWD           10
+
+#define CLK_IR                 11
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h 
b/include/dt-bindings/reset/sun8i-r-ccu.h
new file mode 100644
index 0000000000..4ba64f3d6f
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icen...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+
+#define RST_APB0_IR            0
+#define RST_APB0_TIMER         1
+#define RST_APB0_RSB           2
+#define RST_APB0_UART          3
+/* 4 is reserved for RST_APB0_W1 on A31 */
+#define RST_APB0_I2C           5
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */
-- 
2.14.1

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