> You may try a stress test and toggle the cpufreq frequency settings
> in a fast loop, to see if you can reproduce it faster. Because, waiting 8h
> or more for a crash is not optimal. :)
> If yes, you may try increasing delay between regulator voltage change and
> frequency change. It's a regulator-ramp-delay property in dts, if that
I have no voltage regulator toggling. I only use frequencies that required
1.1V, which is the lowest voltage the regulator provides. I disabled all
the others as they are just short term turbos, thermal can't handle them
I did some stress test with mutliple cores, and it did not show any impact
on how the bug is triggered.
Same to loop forcing frequency toggling.
Are suggestion for some printk that I can get to guess if the crash was
triggered by any specific transition?
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