From: Maxime Ripard <maxime.rip...@bootlin.com>

The FIR filters phase depend on the SoC, so let's move it to our quirks
structure instead of removing them.

Signed-off-by: Maxime Ripard <maxime.rip...@bootlin.com>
Signed-off-by: Paul Kocialkowski <paul.kocialkow...@bootlin.com>
---
 drivers/gpu/drm/sun4i/sun4i_frontend.c | 28 ++++++++++++++++++++------
 drivers/gpu/drm/sun4i/sun4i_frontend.h |  5 +++++
 2 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.c 
b/drivers/gpu/drm/sun4i/sun4i_frontend.c
index 86c5033102b9..4a215d5202e2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_frontend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_frontend.c
@@ -438,12 +438,18 @@ int sun4i_frontend_update_formats(struct sun4i_frontend 
*frontend,
         * I have no idea what this does exactly, but it seems to be
         * related to the scaler FIR filter phase parameters.
         */
-       regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG, 0x400);
-       regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG, 0x400);
-       regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG, 0x400);
-       regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG, 0x400);
-       regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG, 0x400);
-       regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG, 0x400);
+       regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG,
+                    frontend->data->ch_phase[0].horzphase);
+       regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG,
+                    frontend->data->ch_phase[1].horzphase);
+       regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG,
+                    frontend->data->ch_phase[0].vertphase[0]);
+       regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG,
+                    frontend->data->ch_phase[1].vertphase[0]);
+       regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG,
+                    frontend->data->ch_phase[0].vertphase[1]);
+       regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG,
+                    frontend->data->ch_phase[1].vertphase[1]);
 
        /*
         * Checking the input format is sufficient since we currently only
@@ -677,6 +683,16 @@ static const struct dev_pm_ops sun4i_frontend_pm_ops = {
 };
 
 static const struct sun4i_frontend_data sun8i_a33_frontend = {
+       .ch_phase               = {
+               {
+                       .horzphase = 0x400,
+                       .vertphase = { 0x400, 0x400 },
+               },
+               {
+                       .horzphase = 0x400,
+                       .vertphase = { 0x400, 0x400 },
+               },
+       },
        .has_coef_access_ctrl   = true,
 };
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.h 
b/drivers/gpu/drm/sun4i/sun4i_frontend.h
index e332bc1c6b68..0c382c1ddb0f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_frontend.h
+++ b/drivers/gpu/drm/sun4i/sun4i_frontend.h
@@ -115,6 +115,11 @@ struct reset_control;
 struct sun4i_frontend_data {
        bool    has_coef_access_ctrl;
        bool    has_coef_rdy;
+
+       struct {
+               u32     horzphase;
+               u32     vertphase[2];
+       } ch_phase[2];
 };
 
 struct sun4i_frontend {
-- 
2.19.2

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