On Fri, Jan 25, 2019 at 01:28:49AM +0530, Jagan Teki wrote: > Minimum PLL used for MIPI is 500MHz, as per manual, but > lowering the min rate by 300MHz can result proper working > nkms divider with the help of desired dclock rate from > panel driver. > > Signed-off-by: Jagan Teki <[email protected]> > Acked-by: Stephen Boyd <[email protected]>
Going 200MHz below the minimum doesn't seem really reasonable. What is the issue that you are trying to fix here? It looks like it's picking bad dividers, but if that's the case, this isn't the proper fix. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
